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sharc and the sharc logo are registered trademarks of ana log devices, inc. sharc processor adsp-21060/adsp-21060l/adsp-21062/ad sp-21062l/adsp-21060c/adsp-21060lc rev. g information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106 u.s.a. tel : 781.329.4700 www.analog.com fax: 781.461.3113 ? 2010 analog devices, inc. all rights reserved. summary high performance signal processor for communications, graphics and imaging applications super harvard architecture 4 independent buses for dual data fetch, instruction fetch, and nonintrusive i/o 32-bit ieee floating-point computation unitsmultiplier, alu, and shifter dual-ported on-chip sram and integrated i/o peripheralsa complete system-on-a-chip integrated multiprocessing features 240-lead thermally enhanced mqfp_pq4 package, 225-ball plastic ball grid array (pbga), 240-lead hermetic cqfp package rohs compliant packages key featuresprocessor core 40 mips, 25 ns instruction rate, single-cycle instruction execution 120 mflops peak, 80 mflops sustained performance dual data address generators with modulo and bit-reverse addressing) efficient program sequencing with zero-overhead looping: single-cycle loop setup ieee jtag standard 1149.1 test access port and on-chip emulation 32-bit single-precision and 40-bit extended-precision ieee floating-point data formats or 32-bit fixed-point data format figure 1. functional block diagram mult barrel serial ports (2) link ports (6) 4 6 6 36 iop registers (memory mapped) control, status and data buffers i/o processor timer instruction cache addr data data addr addr data addr two independent dual-ported blocks processor port i/o port dual-ported sram jtag test and emulation 7 host port addr bus mux ioa 17 iod 48 multiprocessor interface external port data bus mux 48 32 24 dm address bus pm data bus dm data bus bus connect (px) dag1 32 48 40/32 core processor program sequencer b lock 0 block 1 8 4 32 dag2 8 4 24 32 48-bit pm address bus data controller dma data register file 16 40-bit alu shifter s
rev. g | page 2 of 64 | august 2010 adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc parallel computations single-cycle multiply and alu operations in parallel with dual memory read/write s and instruction fetch multiply with add and subtract for accelerated fft butterfly computation up to 4m bit on-chip sram dual-ported for independent ac cess by core processor and dma off-chip memory interfacing 4 gigawords addressable programmable wait state generation, page-mode dram support dma controller 10 dma channels for transfers between adsp-2106x internal memory and external memory, external peripherals, host processor, serial ports, or link ports background dma transfers at up to 40 mhz, in parallel with full-speed processor execution host processor interface to 16- and 32-bit microprocessors host can directly read/write adsp-2106x internal memory and iop registers multiprocessing glueless connection for scal able dsp multiprocessing architecture distributed on-chip bus arbitration for parallel bus connect of up to six adsp-2106xs plus host six link ports for point-to-point connectivity and array multiprocessing 240 mbps transfer rate over parallel bus 240 mbps transfer rate over link ports serial ports two 40 mbps synchronous serial ports with companding hardware independent transmit and receive functions table 1. adsp-2106x sharc processor family features feature adsp-21060 adsp-21062 adsp-21060l adsp-21062l adsp-21060c adsp-21060lc sram 4m bits 2m bits 4m bits 2m bits 4m bits 4m bits operating voltage 5 v 5 v 3.3 v 3.3 v 5 v 3.3 v instruction rate 33 mhz 40 mhz 33 mhz 40 mhz 33 mhz 40 mhz 33 mhz 40 mhz 33 mhz 40 mhz 33 mhz 40 mhz package mqfp_pq4 pbga mqfp_pq4 pbga mqfp_pq4 pbga mqfp_pq4 pbga cqfp cqfp
adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc rev. g | page 3 of 64 | august 2010 contents summary ............................................................... 1 revision history ...................................................... 3 general description ................................................. 4 sharc family core architecture ............................ 4 memory and i/o interface features ........................... 5 development tools ............................................... 8 evaluation kit ...................................................... 9 designing an emulator -compatible dsp board (target) ........................................................... 9 additional information .......................................... 9 related signal chains ............................................ 9 pin function descriptions ........................................ 10 target board connector for ez-ice probe ................ 13 adsp-21060/adsp-21062 specifications .. ................... 15 operating conditions (5 v) .................................... 15 electrical characteristics (5 v) ................................ 15 internal power dissipation (5 v) ............................. 16 external power dissipation (5 v) ............................ 17 adsp-21060l/adsp-21062l specifications . ................ 18 operating conditions (3.3 v) ................................. 18 electrical characteristics (3.3 v) ............................. 18 internal power dissipation (3.3 v) .......................... 19 external power dissipation (3.3 v) .......................... 20 absolute maximum ratings ................................... 20 esd caution ...................................................... 21 package marking information ................................ 21 timing specifications ........................................... 21 test conditions .................................................. 48 environmental conditions .................................... 51 225-ball pbga ball configuration .............................. 52 240-lead mqfp_pq4/cqfp pin configuration . ........... 54 outline dimensions ................................................ 56 surface-mount design .......................................... 61 ordering guide ..................................................... 62 revision history 8/10rev. f to rev. g added new section, related signal chains ....................... 9 revised table 14 ..................................................... 25 revised table 15 ..................................................... 26 revised table 28 ..................................................... 43 clarification of table 41 title ..................................... 54 clarification of table 42 title ..................................... 55 changes to ordering guide ....................................... 62
rev. g | page 4 of 64 | august 2010 adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc general description the adsp-2106x sharc ? super harvard architecture com- puteris a 32-bit signal processi ng microcomputer that offers high levels of dsp performance. the adsp-2106x builds on the adsp-21000 dsp core to form a complete syst em-on-a-chip, adding a dual-ported on-chip sram and integrated i/o periph- erals supported by a dedicated i/o bus. fabricated in a high speed, low power cmos process, the adsp-2106x has a 25 ns instructio n cycle time and operates at 40 mips. with its on-chip instru ction cache, the processor can execute every instruction in a single cycle. table 2 shows perfor- mance benchmarks for the adsp-2106x. the adsp-2106x sharc represents a new standard of integra- tion for signal computers, combining a high performance floating-point dsp core with integrated, on-chip system fea- tures including up to 4m bit sram memory (see table 1 ), a host processor interface, dma co ntroller, serial ports and link port, and parallel bus connectivity for glueless dsp multiprocessing. the adsp-2106x continues shar cs industry-l eading stan- dards of integration for dsps, combining a high performance 32-bit dsp core with integrated, on-chip system features. the block diagram on page 1 illustrates the following architec- tural features: ? computation units (alu, multiplier and shifter) with a shared data register file ? data address generators (dag1, dag2) ? program sequencer with instruction cache ? pm and dm buses capable of supporting four 32-bit data transfers between me mory and the core at every core pro- cessor cycle ?interval timer ?on-chip sram ? external port for interfacing to off-chip memory and peripherals ? host port and multiprocessor interface ? dma controller ? serial ports and link ports ? jtag test access port sharc family core architecture the adsp-2106x includes the following architectural features of the adsp-21000 family core . the adsp-2106x processors are code- and function-compatible with the adsp-21020. independent, parallel computation units the arithmetic/logic unit (alu), multiplier and shifter all per- form single-cycle instructions. the three units are arranged in parallel, maximizing computatio nal throughput. single multi- function instructions execute pa rallel alu and multiplier oper- ations. these computation units support ieee 32-bit single- precision floating-point, extended precision 40-bit floating- point, and 32-bit fixed-point data formats. data register file a generalCpurpose data register file is used for transferring data between the computation units and the data buses, and for stor- ing intermediate results. this 10-port, 32-register (16 primary, 16 secondary) register file, combined with the adsp-21000 harvard architecture, allows unconstrained data flow between computation units and internal memory. table 2. benchmarks (at 40 mhz) benchmark algorithm speed cycles 1024 point complex fft (radix 4, with reversal) 0.46 s 18,221 fir filter (per tap) 25 ns 1 iir filter (per biquad) 100 ns 4 divide (y/x) 150 ns 6 inverse square root 225 ns 9 dma transfer rate 240 mbytes/s figure 2. adsp-2106x syst em sample configuration 3 reset tag 6 ads bms 1 3 cloc li deice s optional ) cs boot eprom ( optional ) memory- mapped device s optional ) oe data dma deice ( optional ) data addr data ho s ss optional ) cs rd page adrcl ac br1C6 dmar1C2 cli irq2C0 lxcl tcl0 rpba eboot lboot flag3C0 timep lxac lxdat 3 s s s s s optional ) s optional ) pa red hbg hbr dmag1C2 sbts ms3C0 wr data4C0 data addr cs ac we addr 3 s s
adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc rev. g | page 5 of 64 | august 2010 single-cycle fetch of instruction and two operands the adsp-2106x features an enha nced harvard architecture in which the data memory (dm) bu s transfers data and the pro- gram memory (pm) bus transfer s both instructions and data (see figure 1 on page 1 ). with its separate program and data memory buses and on-chip instru ction cache, the processor can simultaneously fetch two operands and an instruction (from the cache), all in a single cycle. instruction cache the adsp-2106x includes an on -chip instruction cache that enables three-bus operation for fe tching an instruction and two data values. the cache is select iveonly the instructions whose fetches conflict with pm bus data accesses are cached. this allows full-speed execution of co re, looped operations such as digital filter multiply-accumulate s and fft butterfly processing. data address generators with hardware circular buffers the adsp-2106xs two data addr ess generators (dags) imple- ment circular data buffers in hardware. circular buffers allow efficient programming of delay li nes and other data structures required in digital signal processing, and are commonly used in digital filters and fourier tran sforms. the two dags of the adsp-2106x contain sufficient regist ers to allow the creation of up to 32 circular buffers (16 pr imary register sets, 16 secondary). the dags automatica lly handle address pointer wraparound, reducing overhead, increasing performance and simplifying implementation. circular buffers can start and end at any mem- ory location. flexible instruction set the 48-bit instruction word accommodates a variety of parallel operations, for concise programming. for example, the adsp-2106x can conditionally ex ecute a multiply, an add, a subtract and a branch, all in a single instruction. memory and i/o interface features the adsp-2106x processors add the following architectural features to the sharc family core. dual-ported on-chip memory the adsp-21062/adsp-21062l contai ns two megabits of on- chip sram, and the adsp -21060/adsp-21060l contains 4m bits of on-chip sram. the internal memory is organized as two equal sized blocks of 1m bit each for the adsp-21062/ adsp-21062l and two equal sized blocks of 2m bits each for the adsp-21060/adsp-21060l. each can be configured for dif- ferent combinations of code and data storage. each memory block is dual-ported for single-cycle, independent accesses by the core processor and i/o proc essor or dma controller. the dual-ported memory and separate on-chip buses allow two data transfers from the core and one from i/o, all in a single cycle. on the adsp-21062/adsp-21062l, th e memory can be config- ured as a maximum of 64k word s of 32-bit data, 128k words of 16-bit data, 40k words of 48-bit in structions (or 40-bit data), or combinations of different word sizes up to two megabits. all of the memory can be accessed as 16-bit, 32-bit, or 48-bit words. on the adsp-21060/adsp-21060l, th e memory can be config- ured as a maximum of 128k words of 32-bit data, 256k words of 16-bit data, 80k words of 48-bit in structions (or 40-bit data), or combinations of different word sizes up to four megabits. all of the memory can be accessed as 16-bit, 32-bit or 48-bit words. a 16-bit floating-point storage format is supported, which effec- tively doubles the amount of data that can be stored on-chip. conversion between the 32-bit floating-point and 16-bit float- ing-point formats is done in a single instruction. while each memory block can store combinations of code and data, accesses are most efficien t when one block stores data, using the dm bus for transfers, and the other block stores instructions and data, using the pm bus for transfers. using the dm bus and pm bus in this way, with one dedicated to each memory block, assures single-c ycle execution with two data transfers. in this ca se, the instruction must be available in the cache. single-cycle execution is also maintained when one of the data operands is transferred to or from off-chip, via the adsp-2106xs external port. on-chip memory and peripherals interface the adsp-2106xs external port provides the processors inter- face to off-chip memory and pe ripherals. the 4-gigaword off- chip address space is included in the adsp-2106xs unified address space. the separate on -chip busesfor pm addresses, pm data, dm addresses, dm data, i/o addresses, and i/o dataare multiplexed at the external port to create an external system bus with a single 32-bit address bus and a single 48-bit (or 32-bit) data bus. addressing of external memory devices is facilitated by on-chip decoding of high-order address lines to generate memory bank select signals. separa te control lines are also generated for sim- plified addressing of page -mode dram. the adsp-2106x provides programmable memory wait states and external mem- ory acknowledge controls to a llow interfacing to dram and peripherals with variable access, hold and disable time requirements. host processor interface the adsp-2106xs host interface allows easy co nnection to standard microprocessor buses, both 16-bit and 32-bit, with lit- tle additional hardware required. asynchronous transfers at speeds up to the full clock rate of the processor are supported. the host interface is accessed through the adsp-2106xs exter- nal port and is memory-mapped in to the unified address space. four channels of dma are availabl e for the host interface; code and data transfers are accomp lished with low software overhead. the host processor requests the adsp-2106xs external bus with the host bus request (hbr ), host bus grant (hbg ), and ready (redy) signals. the host can di rectly read and write the inter- nal memory of the adsp- 2106x, and can access the dma channel setup and mailbox register s. vector interrupt support is provided for efficient exec ution of host commands.
rev. g | page 6 of 64 | august 2010 adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc figure 3. shared memory multiprocessing system addr 3 1C0 cpa bms c o n t r o l ad s p-2106x #1 5 control ad s p-2106x #2 addr 3 1C0 control ad s p-2106x # 3 5 id2C0 reset rpba clkin id2C0 reset rpba id2C0 reset rpba clkin ad s p-2106x #6 ad s p-2106x #5 ad s p-2106x #4 clock re s et addr data ho s tproce ss or interface (optional) ack global memory and peripheral (optional) oe addr data cs addr data boot eprom (optional) rdx ms3C0 sbts cs ack addr 3 1C0 clkin 3 001 page 3 010 3 011 br1 br2C6 redy hbg hbr cs we wrx 5 c o n t r o l a d d r e s s d a t a c o n t r o l a d d r e s s d a t a data47C0 br1C2, br4C6 br3 data47C0 br1, br3C6 br2 data47C0 bu s priority cpa
adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc rev. g | page 7 of 64 | august 2010 dma controller the adsp-2106xs on-chip dma controller allows zero-over- head data transfers without pr ocessor intervention. the dma controller operates independently and invisibly to the processor core, allowing dma operations to occur while the core is simul- taneously executing its program instructions. dma transfers can occur between the adsp-2106xs internal memory and external memory, external peripherals, or a host processor. dma transfers can also occur between the adsp- 2106xs internal memory and its se rial ports or link ports. dma transfers between external memo ry and external peripheral devices are another option. external bus packing to 16-, 32-, or 48-bit words is perf ormed during dma transfers. ten channels of dma are available on the adsp-2106xtwo via the link ports, four via the serial ports, and four via the processors external port (for either host processor, other adsp-2106xs, memory, or i/o tran sfers). four additional link port dma channels are shared with serial port 1 and the exter- nal port. programs can be downloaded to the adsp-2106x using dma transfers. asynchrono us off-chip peripherals can control two dma channels using dma request/grant lines (dmar1C2 , dmag1C2 ). other dma features include inter- rupt generation upon completion of dma transfers and dma chaining for automatic linked dma transfers. multiprocessing the adsp-2106x offers powerful fe atures tailored to multipro- cessor dsp systems. the unified address space (see figure 4 ) allows direct interprocessor accesses of each adsp-2106xs internal memory. distributed bus arbitration logic is included on-chip for simple, glueless conne ction of systems containing up to six adsp-2106xs and a host processor. master processor changeover incurs only one cycle of overhead. bus arbitration is selectable as either fixed or ro tating priority. bus lock allows indivisible read-modify-write sequences for semaphores. a vec- tor interrupt is provided for interprocessor commands. maxi- mum throughput for interpro cessor data transfer is 240m bytes/s over the link ports or external port. broadcast writes allow simultaneous tr ansmission of data to all adsp-2106xs and can be used to implement reflective semaphores. figure 4. memory map 0x0004 0000 0x0010 0000 0x000 8 0000 0x001 8 0000 0x0012 0000 0x002 8 0000 0x00 38 0000 0x0000 0000 0x0002 0000 0x0040 0000 bank 1 m s 0 bank 2 m s 1 bank 3 m s 2 m s3 iop regi s ter s s hort word addre ss ing (16-bit data word s ) normal word addre ss ing ( 3 2-bit data word s 4 8 -bit in s truction word s ) addre ss bank 0 s dram (optional) 0x0fff ffff nonbanked note: bank s ize s are s elected by ms ize bit s in the s y s con regi s ter 0x00 3 0 0000 internal memory s pace multiproce ss or memory s pace addre ss internal memory s pace with id = 001 0 x 00 3 f ffff external memory s pace internal memory s pace with id = 010 internal memory s pace with id = 011 internal memory s pace with id = 100 internal memory s pace with id = 101 internal memory s pace with id = 110 broadca s twrite to all ad s p-21061s
rev. g | page 8 of 64 | august 2010 adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc link ports the adsp-2106x features six 4-bit link ports that provide addi- tional i/o capabilities. the link ports can be clocked twice per cycle, allowing each to transfer ei ght bits of data per cycle. link- port i/o is especially useful for point-to-point interprocessor communication in mult iprocessing systems. the link ports can operate inde pendently and simultaneously, with a maximum data throughput of 240m bytes/s. link port data is packed into 32- or 48-bit words, and can be directly read by the core processor or dma- transferred to on-chip memory. each link port has its own double-buffered input and output registers. clock/acknowledge handshaking controls link port transfers. transfers are programm able as either transmit or receive. program booting the internal memory of the ad sp-2106x can be booted at sys- tem power-up from an 8-bit eprom, a host processor, or through one of the link ports. se lection of the boot source is controlled by the bms (boot me mory select), eboot (eprom boot), and lboot (link/host bo ot) pins. 32-bit and 16-bit host processors can be used for bo oting. the processor also sup- ports a no-boot mode in which instruction execution is sourced from the external memory. development tools the adsp-2106x is supported by a complete set of crosscore ? ? software development tools, including analog devices emulators and visualdsp++ ? ? development environ- ment. the same emulator hardwa re that supports other sharc processors also fully emulates the adsp-2106x. the visualdsp++ project management environment lets pro- grammers develop and debug an application. this environment includes an easy to use assembler (which is based on an alge- braic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accura te instruction-level simulator, a c/c++ compiler, and a c/c++ runtime library that includes dsp and mathematical functions. a key point for these tools is c/c++ code efficiency. the compiler ha s been developed for efficient translation of c/c++ code to dsp assembly. the adsp-2106x sharc dsp has architectural feat ures that improve the effi- ciency of compiled c/c++ code. the visualdsp++ debugger has a number of important fea- tures. data visualization is enhanced by a plotting package that offers a significant level of flexibility. this graphical representa- tion of user data enables the programmer to quickly determine the performance of an algorithm. as algorithms grow in com- plexity, this capability can have increasing significance on the designers development schedule, increasing productivity. sta- tistical profiling enables the pr ogrammer to nonintrusively poll the processor as it is running the program. this feature, unique to visualdsp++, enables the software developer to passively gather important code executio n metrics without interrupting the real-time characteristics of the program. essentially, the developer can identify bottlenecks in software quickly and effi- ciently. by using the profiler , the programmer can focus on those areas in the program that impact performance and take corrective action. debugging both c/c++ and assembly programs with the visualdsp++ debugger, programmers can: ? view mixed c/c++ and assembly code (interleaved source and object information) ? insert breakpoints ? set conditional breakpoints on registers, memory, and stacks ? trace instruction execution ? perform linear or statistical profiling of program execution ? fill, dump, and graphically plot the contents of memory ? perform source level debugging ? create custom debugger windows the visualdsp++ idde lets programmers define and manage dsp software development. its di alog boxes and property pages let programmers configure and manage all of the adsp-2106x development tools, including the color syntax highlighting in the visualdsp++ editor. this capability permits: ? control in how the development tools process inputs and generate outputs ? maintenance of a one-to-one correspondence with the tools command line switches the visualdsp++ kernel (vdk) incorporates scheduling and resource management tailored sp ecifically to address the mem- ory and timing constraints of dsp programming. these capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning when developing new application code. the vdk features include threads, critical and unschedule d regions, semaphores, events, and device flags. the vdk also supports priority-based, pre- emptive, cooperative, and time-s liced scheduling approaches. in addition, the vdk was designed to be scalable. if the application does not use a specific feature, the support code for that feature is excluded from the target system. because the vdk is a library, a developer can decide whether to use it or not. the vdk is integrated into the visualdsp++ development environment, but ca n also be used via standard command line tools. when the vdk is used, the development environment assists th e developer with many error-prone tasks and assists in managi ng system resources, automating the gen- eration of various vdk-based objects, and vi sualizing the system state, when debugging an application that uses the vdk. use the expert linker to visually manipulate the placement of code and data on the embedded system. view memory utiliza- tion in a color-coded graphical form, easily move code and data to different areas of the dsp or external memory with a drag of the mouse, and examine run-time stack and heap usage. the ? crosscore is a registered trademark of analog devices, inc. ? visualdsp++ is a registered trademark of analog devices, inc.
adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc rev. g | page 9 of 64 | august 2010 expert linker is fully compatible with existing linker definition file (ldf), allowing the developer to move between the graphi- cal and textual environments. in addition to the software development tools available from analog devices, third parties pr ovide a wide range of tools sup- porting the sharc processor family. third party software tools include dsp libraries, real-tim e operating systems, and block diagram design tools. evaluation kit analog devices offers a range of ez-kit lite ? ? evaluation plat- forms to use as a cost-effective method to learn more about developing or prototyping appl ications with analog devices processors, platforms, and softwa re tools. each ez-kit lite includes an evaluation board alon g with an evaluation suite of the visualdsp++ development and debugging environment with the c/c++ compiler, assemble r, and linker. also included are sample application programs, power supply, and a usb cable. all evaluation versions of the software tools are limited for use only with the ez-kit lite product. the usb controller on the ez-k it lite board connects the board to the usb port of th e users pc, enabling the visualdsp++ evaluation suite to emulate the on-board proces- sor in-circuit. this permits the customer to download, execute, and debug programs for the ez-kit lite system. it also allows in-circuit programming of the on-board flash device to store user-specific boot co de, enabling the board to run as a stand- alone unit, without being connected to the pc. with a full version of visualdsp ++ installed (sold separately), engineers can develop software fo r the ez-kit lite or any cus- tom-defined system. connecting an analog devices jtag emulator to the ez-kit lite bo ard enables high speed, nonin- trusive emulation. designing an emulator-compatible dsp board (target) the analog devices family of emulators are tools that every dsp developer needs to test an d debug hardware and software systems. analog devices has supp lied an ieee 1149.1 jtag test access port (tap) on each jtag dsp. nonintrusive in-circuit emulation is assured by the use of the processors jtag inter- facethe emulator does not affect target system loading or tim- ing. the emulator uses the tap to access the internal features of the dsp, allowing the developer to load code, set breakpoints, observe variables, observe memo ry, and examine registers. the dsp must be halted to send da ta and commands, but once an operation has been completed by the emulator, the dsp system is set running at full speed with no impact on system timing. to use these emulators, the targ et board must include a header that connects the dsps jtag port to the emulator. for details on target board desi gn issues including mechanical layout, single processor conn ections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the ee-68: analog devices jtag emulation technical reference on the analog devices website (www.analog.com) use site search on ee-68. this document is updated regularly to keep pace with improvements to emulator support. additional information this data sheet provides a gene ral overview of the adsp-2106x architecture and functionality. for detailed information on the adsp-21000 family core architectu re and instruction set, refer to the adsp-2106x sharc users manual , revision 2.1. related signal chains a signal chain is a series of signal-c onditioning electronic com- ponents that receive input (data acquired from sampling either real-time phenomena or from stor ed data) in tandem, with the output of one portion of the ch ain supplying input to the next. signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. for more information about this term and related topics, see the signal chain entry in the glossary of ee terms on the analog devices website. analog devices eases signal proc essing system development by providing signal processing comp onents that are designed to work together well. a tool fo r viewing relationships between specific applications and related components is available on the www.analog.com website. the application signal chains page in the circuits from the lab tm site ( http://www.analog.com/signalchains ) provides: ? graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications ? drill down links for components in each chain to selection guides and application information ? reference designs applying be st practice design techniques ? ez-kit lite is a registered trademark of analog devices, inc.
rev. g | page 10 of 64 | august 2010 adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc pin function descriptions the adsp-2106x pin defi nitions are listed be low. inputs identi- fied as synchronous (s) must m eet timing requirements with respect to clkin (or with respect to tck for tms, tdi). inputs identified as asynchronous (a) can be asserted asynchro- nously to clkin (or to tck for trst ). unused inputs should be tied or pulled to vdd or gnd, except for addr31C0, data47C0, flag3C 0, and inputs that have internal pull-up or pu ll-down resistors (cpa , ack, dtx, drx, tclkx, rclkx, lxdat3C0, lxclk, lxack, tms, and tdi)these pins can be left floating. these pins have a logic-level hold circuit that pr events the input from floating internally. table 3. pin descriptions pin type function addr31C0 i/o/t external bus address. the adsp-2106x outputs addresses for ex ternal memory and peripherals on these pins. in a multiprocessor system, the bus master outp uts addresses for read/write of the internal memory or iop registers of other adsp-2106xs. the adsp-2106x inputs addresses when a host processor or multi- processing bus master is reading or writing its internal memory or iop registers. data47C0 i/o/t external bus data. the adsp-2106x inputs and outputs data and instructions on these pins. 32-bit single- precision floating-point data and 32-bit fixed-point data is transferred over bits 47C16 of the bus. 40-bit extended-precision floating- point data is transferred over bits 47C8 of the bus. 16-bit short word data is transferred over bits 31C16 of the bus. in prom boot mo de, 8-bit data is transferred over bits 23C16. pull-up resistors on unused data pins are not necessary. ms3C0 o/t memory select lines. these lines are asserted (low) as chip selects for the corresponding banks of external memory. memory bank size must be defined in the adsp-2106xs system control register (syscon). the ms3C0 lines are decoded memory address lines that change at the same time as the other address lines. when no external memory access is occurring, the ms3C0 lines are inactive; they are active however when a conditional memory access instruction is executed, whether or not the condition is true. ms0 can be used with the page signal to implement a bank of dram me mory (bank 0). in a multiprocessing system the ms3C0 lines are output by the bus master. rd i/o/t memory read strobe. this pin is asserted (low) when the adsp-2106x reads from external memory devices or from the internal memory of other adsp-2106xs. external devices (including other adsp-2106xs) must assert rd to read from the adsp-2106xs internal memory. in a multiprocessing system, rd is output by the bus master and is input by all other adsp-2106xs. wr i/o/t memory write strobe. this pin is asserted (low) when the adsp-2106x writes to external memory devices or to the internal memory of other adsp -2106xs. external devices must assert wr to write to the adsp- 2106xs internal memory. in a multiprocessing system, wr is output by the bus master and is input by all other adsp-2106xs. page o/t dram page boundary. the adsp-2106x asserts this pin to signal that an external dram page boundary has been crossed. dram page size must be defined in the adsp-2106xs memory control register (wait). dram can only be implemented in external memory bank 0; the page signal can only be activated for bank 0 accesses. in a multiprocessing system, page is output by the bus master adrclk o/t clock output reference. in a multiprocessing system, adrclk is output by the bus master. sw i/o/t synchronous write select. this signal is used to interface the adsp-2106x to synchronous memory devices (including other adsp-2106xs). the adsp-2106x asserts sw (low) to provide an early indication of an impending write cycle, which can be aborted if wr is not later asserted (e.g., in a conditional write instruction). in a multiprocessing system, sw is output by the bus master and is input by all other adsp-2106xs to determine if the multiprocessor memory access is a read or write. sw is asserted at the same time as the address output. a host pr ocessor using synchronous writes must assert this pin when writing to the adsp-2106x(s). a = asynchronous, g = ground, i = input, o = output, p = power supply, s = synchronous, (a/d) = active drive, (o/d) = open drai n, t = three-state (when sbts is asserted, or when the adsp-2106x is a bus slave)
adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc rev. g | page 11 of 64 | august 2010 ack i/o/s memory acknowledge. external devices can deassert ack (low) to add wait states to an external memory access. ack is used by i/o devices, memory controllers , or other peripherals to ho ld off completion of an external memory access. the adsp-2106x deasserts ac k as an output to add waitstates to a synchronous access of its internal memory. in a multiprocessing sy stem, a slave adsp-2106x deasserts the bus masters ack input to add wait state(s) to an access of its inte rnal memory. the bus master has a keeper latch on its ack pin that maintains the input at the level to which it was last driven. sbts i/s suspend bus three-state. external devices can assert sbts (low) to place the external bus address, data, selects, and strobes in a high impedance state for the following cycle. if the adsp-2106x attempts to access external memory while sbts is asserted, the processor will halt and the memory access will not be completed until sbts is deasserted. sbts should only be used to recover from host processor/adsp-2106x deadlock, or used with a dram controller. irq2C0 i/a interrupt request lines. may be either edge-triggered or level-sensitive. flag3C0 i/o/a flag pins. each is configured via control bits as either an in put or output. as an input, they can be tested as a condition. as an output, they can be used to signal external peripherals. timexp o timer expired. asserted for four cycles when the timer is enabled and tcount decrements to zero. hbr i/a host bus request. this pin must be asserted by a host proc essor to request control of the adsp-2106xs external bus. when hbr is asserted in a multiprocessing system , the adsp-2106x that is bus master will relinquish the bus and assert hbg . to relinquish the bus, the adsp-2106x places the address, data, select and strobe lines in a high impedance state. hbr has priority over all adsp -2106x bus requests br6C1 in a multiprocessing system. hbg i/o host bus grant. acknowledges a bus request, indicating that the host processor may take control of the external bus. hbg is asserted (held low) by the adsp-2106x until hbr is released. in a multiprocessing system, hbg is output by the adsp-2106x bus master and is monitored by all others. cs i/a chip select. asserted by host processor to select the adsp-2106x. redy o (o/d) host bus acknowledge. the adsp-2106x deasserts redy (low) to a dd wait states to an asynchronous access of its internal memory or iop registers by a host. this pin is an open-drain output (o/d) by default; it can be programmed in the adredy bit of the syscon register to be active drive (a/d). redy will only be output if the cs and hbr inputs are asserted. dmar2C1 i/a dma request 1 (dma channel 7) and dma request 2 (dma channel 8). dmag2C1 o/t dma grant 1 (dma channel 7) and dma grant 2 (dma channel 8). br6C1 i/o/s multiprocessing bus requests. used by multiprocessing adsp-2106xs to arbitrate for bus master-ship. an adsp-2106x only drives its own br x line (corresponding to the value of its id2-0 inputs) and monitors all others. in a multiprocessor system with less than six adsp-2106xs, the unused br x pins should be pulled high; the processors own br x line must not be pulled high or low because it is an output. id2C0 o (o/d) multiprocessing id. determines which multiprocessing bus request (br1 C br6 ) is used by adsp-2106x. id = 001 corresponds to br1 , id = 010 corresponds to br2 , etc. id = 000 in single-processor systems. these lines are a system configuration selection that should be hardwired or changed at reset only. rpba i/s rotating priority bus arbitration select. when rpba is high, rotating priority for multiprocessor bus arbitration is selected. when rpba is low, fixed priori ty is selected. this signal is a system configuration selection that must be set to the same value on every adsp-2106x. if the value of rpba is changed during system operation, it must be changed in the same clkin cycle on every adsp-2106x. cpa i/o (o/d) core priority access. asserting its cpa pin allows the core processor of an adsp-2106x bus sla ve to interrupt background dma transfers and gain access to the external bus. cpa is an open drain output that is connected to all adsp-2106xs in the system. the cpa pin has an internal 5 k pull-up resistor. if core access priority is not required in a system, the cpa pin should be left unconnected. dtx o data transmit (serial ports 0, 1). each dt pin has a 50 k internal pull-up resistor. drx i data receive (serial ports 0, 1). each dr pin has a 50 k internal pull-up resistor. tclkx i/o transmit clock (serial ports 0, 1). each tclk pin has a 50 k internal pull-up resistor. rclkx i/o receive clock (serial ports 0, 1). each rclk pin has a 50 k internal pull-up resistor. table 3. pin descriptions (continued) pin type function a = asynchronous, g = ground, i = input, o = output, p = power supply, s = synchronous, (a/d) = active drive, (o/d) = open drai n, t = three-state (when sbts is asserted, or when the adsp-2106x is a bus slave)
rev. g | page 12 of 64 | august 2010 adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc tfsx i/o transmit frame sync (serial ports 0, 1). rfsx i/o receive frame sync (serial ports 0, 1). lxdat3C0 i/o link port data (link ports 0C5). each lxdat pin has a 50 k internal pull-down resistor that is enabled or disabled by the lpdrd bi t of the lcom register. lxclk i/o link port clock (link ports 0C5). each lxclk pin has a 50 k internal pull-down resistor that is enabled or disabled by the lpdrd bi t of the lcom register. lxack i/o link port acknowledge (link ports 0C5). each lxack pin has a 50 k internal pull-down resistor that is enabled or disabled by the lpdrd bit of the lcom register. eboot i eprom boot select. when eboot is high, the adsp-2106x is configured for booting from an 8-bit eprom. when eboot is low, the lboot and bms inputs determine booting mode. see the table in the bms pin description below. this signal is a system configuration selection that should be hardwired. lboot i link boot. when lboot is high, the adsp-2106x is configured for link port booting. when lboot is low, the adsp-2106x is configured for host processor booting or no booting. see the table in the bms pin description below. this signal is a system configuration selection that should be hardwired. bms i/ot boot memory select. output : used as chip select for boot eprom devices (when eboot = 1, lboot = 0). in a multiprocessor system, bms is output by the bus master. input: when low, indicates that no booting will occur and that adsp-2106x will begin executing instru ctions from external memory. see table below. this input is a system configuration selection that should be hardwired. *three-statable only in eprom boot mode (when bms is an output). eboot lboot bms booting mode 1 0 output eprom (connect bms to eprom chip select.) 0 0 1 (input) host processor 0 1 1 (input) link port 0 0 0 (input) no booting. processor executes from external memory. 010 (input) reserved 1 1 x (input) reserved clkin i clock in. external clock input to the adsp-2106x. the instru ction cycle rate is equal to clkin. clkin should not be halted, changed, or operated below the minimum specified frequency. reset i/a processor reset. resets the adsp-2106x to a known state an d begins program execution at the program memory location specified by the ha rdware reset vector address. this input must be asserted (low) at power-up. tck i test clock (jtag). provides an asynchronous clock for jtag boundary scan. tms i/s test mode select (jtag). used to control the test state machine. tms has a 20 k internal pull-up resistor. tdi i/s test data input (jtag). provides serial data for the boundary scan logic. tdi has a 20 k internal pull-up resistor. tdo o test data output (jtag). serial scan output of the boundary scan path. trst i/a test reset (jtag). resets the test state machine. trst must be asserted (pulsed low) after power-up or held low for proper operation of the adsp-2106x. trst has a 20 k internal pull-up resistor. emu o emulation status. must be connected to the adsp-2106x ez-ice target board connector only. icsa o reserved, leave unconnected. vdd p power supply; nominally 5.0 v dc for 5 v devices or 3.3 v dc for 3.3 v devices. (30 pins). gnd g power supply return. (30 pins). nc do not connect. reserved pins which must be left open and unconnected. table 3. pin descriptions (continued) pin type function a = asynchronous, g = ground, i = input, o = output, p = power supply, s = synchronous, (a/d) = active drive, (o/d) = open drai n, t = three-state (when sbts is asserted, or when the adsp-2106x is a bus slave)
adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc rev. g | page 13 of 64 | august 2010 target board connector for ez-ice probe the adsp-2106x ez-ice ? emulator uses the ieee 1149.1jtag test access port of the adsp-2106x to monitor and control the target board processor during emulation. the ez-ice probe requires the adsp-2106xs clkin, tms, tck, trst , tdi, tdo, emu , and gnd signals be made accessible on the target system via a 14-pi n connector (a 2-row 7-pin strip header) such as that shown in fi gure 5. the ez-ice probe plugs directly onto this connector for chip-on-board emulation. you must add this connector to your target board design if you intend to use the adsp-2106x ez -ice. the total trace length between the ez-ice connector an d the furthest device sharing the ez-ice jtag pin should be limited to 15 inches maximum for guaranteed operation. this length restriction must include ez-ice jtag signals that ar e routed to one or more adsp-2106x devices, or a comb ination of adsp-2106x devices and other jtag devices on the chain. the 14-pin, 2-row pin strip header is keyed at the pin 3 loca- tionpin 3 must be removed from the header. the pins must be 0.025 inch square and at least 0. 20 inch in length. pin spacing should be 0.1 0.1 inches. pin strip headers are available from vendors such as 3m, mckenzie , and samtec. the btms, btck, btrst , and btdi signals are provid ed so that the test access port can also be used for board-level testing. when the connector is not being used for emulation, place jumpers between the bxxx pins and the xxx pins as shown in figure 5 . if you are not going to use the test access port for board testing, tie btrst to gnd and tie or pull up btck to v dd . the trst pin must be asserted (pulsed low) after power- up (through btrst on the connector) or held low for proper operation of the adsp-2106x. none of the bxxx pins (pins 5, 7, 9, and 11) are connected on the ez-ice probe. the jtag signals are terminated on the ez-ice probe as shown in table 4 . figure 6 shows jtag scan path co nnections for systems that contain multiple adsp-2106x processors. connecting clkin to pin 4 of the ez-ice header is optional. the emulator only uses clkin wh en directed to perform oper- ations such as starting, stoppi ng, and single-stepping multiple adsp-2106xs in a synchronous manner. if you do not need these operations to occur synchronously on the multiple proces- sors, simply tie pin 4 of th e ez-ice header to ground. if synchronous multiprocessor operations are needed and clkin is connected, clock skew between the multiple adsp-2106x processors and th e clkin pin on the ez-ice header must be minimal. if the skew is too large, synchronous operations may be off by one or more cycles between proces- sors. for synchronous multipro cessor operation tck, tms, clkin, and emu should be treated as cr itical signals in terms of skew, and should be laid ou t as short as possible on your board. if tck, tms, and clkin are driving a large number of adsp-2106xs (more than eight) in your syst em, then treat them as a clock tree using multiple drivers to minimize skew. (see figure 7 and jtag clock tree and clock distribution in the high frequency design co nsiderations section of the adsp-2106x users manual , revision 2.1.) if synchronous multiprocessor op erations are not needed (i.e., clkin is not connected), just use appropriate parallel termina- tion on tck and tms. tdi, tdo, emu and trst are not critical signals in terms of skew. for complete information on the sharc ez-ice, see the adsp-21000 family jtag ez-ice user's guide and reference . figure 5. target board connector for adsp-2106x ez-ice emulator (jumpers in place) top view 1 3 8 3 s s s s s signal termination tms driven through 22 resistor (16 ma driver) tck driven at 10 mhz through 22 resistor (16 ma driver) trst 1 1 trst is driven low until the ez-ice probe is turned on by the emulator at software start-up. after software st art-up, is driven high. active low driven through 22 resistor (16 ma driver) (pulled-up by on-chip 20 k resistor) tdi driven by 22 resistor (16 ma driver) tdo one ttl load, split termination (160/220) clkin one ttl load, split termination (160/220) emu active low 4.7 k pull-up resistor, one ttl load (open-drain output from the dsp)
rev. g | page 14 of 64 | august 2010 adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc figure 6. jtag scan path connections for multiple adsp-2106x systems figure 7. jtag clocktree for multiple adsp-2106x systems t r s t e m u t r s t ad s p-2106x #1 jtag device (optional) ad s p-2106x n tdi ez-ice jtag connector other jtag controller optional t c k t m s emu tm s tck tdo clkin trst t c k t m s t c k t m s tdi tdo tdi tdo tdo tdi t r s t t r s t e m u e m u s y s tem clkin emu 5k v * tdi tdo 5k v tdi emu tm s tck tdo trst clkin *open-drain driver or equivalent, i.e., tdi tdo tdi tdo tdi tdo tdi tdo tdi tdo *
adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc rev. g | page 15 of 64 | august 2010 adsp-21060/adsp-210 62 specifications note that component specificat ions are subject to change without notice. operating conditions (5 v) electrical characteristics (5 v) a grade c grade k grade parameter description min max min max min max unit v dd supply voltage 4.75 5.25 4.75 5.25 4.75 5.25 v t case case operating temperature C40 +85 C40 +100 C40 +85 c v ih 1 1 1 applies to input and bidirectio nal pins: data47C0, addr31C0, rd , wr , sw , ack, sbts , irq 2C0, flag3C0, hgb , cs , dmar1 , dmar2 , br6C1 , id2C0, rpba, cpa , tfs0, tfs1, rfs0, rfs1, lxdat3C0, lx clk, lxack, eboot, lboot, bms , tms, tdi, tck, hbr , dr0, dr1, tclk0, tclk1, rclk0, rclk1. high level input voltage @ v dd = max 2.0 v dd + 0.5 2.0 v dd + 0.5 2.0 v dd + 0.5 v v ih 2 2 2 applies to input pins: clkin, reset , trst. high level input voltage @ v dd = max 2.2 v dd + 0.5 2.2 v dd + 0.5 2.2 v dd + 0.5 v v il 1, 2 low level input voltage @ v dd = min C0.5 +0.8 C0.5 +0.8 C0.5 +0.8 v parameter description test conditions min max unit v oh 1, 2 high level output voltage @ v dd = min, i oh = C2.0 ma 4.1 v v ol 1, 2 low level output voltage @ v dd = min, i ol = 4.0 ma 0.4 v i ih 3, 4 high level input current @ v dd = max, v in = v dd max 10 a i il 3 low level input current @ v dd = max, v in = 0 v 10 a i ilp 4 low level input current @ v dd = max, v in = 0 v 150 a i ozh 5, 6, 7, 8 three-state leakage current @ v dd = max, v in = v dd max 10 a i ozl 5, 9 three-state leakage current @ v dd = max, v in = 0 v 10 a i ozhp 9 three-state leakage current @ v dd = max, v in = v dd max 350 a i ozlc 7 three-state leakage current @ v dd = max, v in = 0 v 1.5 ma i ozla 10 three-state leakage current @ v dd = max, v in = 1.5 v 350 a i ozlar 8 three-state leakage current @ v dd = max, v in = 0 v 4.2 ma i ozls 6 three-state leakage current @ v dd = max, v in = 0 v 150 a c in 11, 12 input capacitance f in = 1 mhz, t case = 25c, v in = 2.5 v 4.7 pf 1 applies to output and bidirectional pins: data 47C0, addr31-0, ms3C0 , rd , wr , page, adrclk, sw , ack, flag3C0, timexp, hbg , redy, dmag1 , dmag2 , br6C1 , cpa, dt0, dt1, tclk0, tclk1, rclk0, rclk1, tfs0, tfs1, rfs0, rfs1, lxdat3C0, lxclk, lxack, bms , tdo, emu , icsa. 2 see output drive currents for ty pical drive current capabilities. 3 applies to input pins: ack, sbts , irq2C0 , hbr , cs , dmar1 , dmar2 , id2C0, rpba, eboot, lboot, clkin, reset , tck. 4 applies to input pins with internal pull-ups: dr0, dr1, trst , tms, tdi. 5 applies to three-statable pin s: data47C0, addr31C0, ms3C0 , rd , wr , page, adrclk, sw , ack, flag3C0, hbg , redy, dmag1 , dmag2 , bms , br6C1 , tfsx, rfsx, tdo, emu . (note that ack is pulled up internally with 2 k during reset in a multiprocessor system, when id2C0 = 001 and another adsp-2106x is not requesting bus mastership.) 6 applies to three-statable pins with internal pu ll-ups: dt0, dt1, tclk0, tclk1, rclk0, rclk1. 7 applies to cpa pin. 8 applies to ack pin when pulle d up. (note that ack is pulled up internally with 2 k during reset in a multiproc essor system, when id2C0 = 001 and another adsp-2106xl is not requesting bus mastership). 9 applies to three-statable pins with inte rnal pull-downs: lxdat3C0, lxclk, lxack. 10 applies to ack pin when keeper latch enabled. 11 applies to all signal pins. 12 guaranteed but not tested.
rev. g | page 16 of 64 | august 2010 adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc internal power dissipation (5 v) these specifications apply to th e internal power portion of v dd only. for a complete discussion of the code used to measure power dissipation, see the technical note sharc power dissi- pation measurements. specifications are based on the operating scenarios. to estimate power consumption fo r a specific application, use the following equation where% is the amount of time your pro- gram spends in that state: %peak i ddinpeak +%high i ddinhigh +%low i ddinlow + %idle i ddidle = power consumption operation peak activity (i ddinpeak ) high activity (i ddinhigh ) low activity (i ddinlow ) instruction type multifunction multifunction single function instruction fetch cache internal memory internal memory core memory access 2 per cycle (dm and pm) 1 per cycle (dm) none internal memory dma 1 per cycle 1 per 2 cycles 1 per 2 cycles parameter test conditions max units i ddinpeak supply current (internal) 1 t ck = 30 ns, v dd = max t ck = 25 ns, v dd = max 745 850 ma ma i ddinhigh supply current (internal) 2 t ck = 30 ns, v dd = max t ck = 25 ns, v dd = max 575 670 ma ma i ddinlow supply current (internal) 2 t ck = 30 ns, v dd = max t ck = 25 ns, v dd = max 340 390 ma ma i ddidle supply current (idle) 3 v dd = max 200 ma 1 the test program used to measure i ddinpeak represents worst case processor operation and is not sustaina ble under normal application co nditions. actual internal power measurements made using typical appl ications are less than specified. 2 i ddinhigh is a composite average based on a range of high activity code. i ddinlow is a composite average based on a range of low activity code. 3 idle denotes adsp-2106x state duri ng execution of idle instruction.
adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc rev. g | page 17 of 64 | august 2010 external power dissipation (5 v) total power dissipation has two components, one due to inter- nal circuitry and one due to the switching of external output drivers. internal power dissipation is dependent on the instruc- tion execution sequence and the data operands involved. internal power dissipation is calculated in the following way: p int = i ddin v dd the external component of total power dissipation is caused by the switching of output pins. its magnitude depends on: ? the number of output pins th at switch during each cycle (o) ? the maximum frequency at which they can switch (f) ? their load capacitance (c) ? their voltage swing (v dd ) and is calculated by: p ext = o c v dd 2 f the load capacitance should in clude the processors package capacitance (cin). the switchin g frequency includes driving the load high and then back low. address and data pins can drive high and low at a maximum rate of 1/(2t ck ). the write strobe can switch every cycle at a frequency of 1/t ck . select pins switch at 1/(2t ck ), but selects can switch on each cycle. example: estimate p ext with the following assumptions: ? a system with one bank of external data memory ram (32-bit) ? four 128k 8 ram chips are used, each with a load of 10 pf ? external data memory writes occur every other cycle, a rate of 1/(4t ck ), with 50% of the pins switching ? the instruction cycle rate is 40 mhz (t ck = 25 ns) the p ext equation is calculated for each class of pins that can drive: a typical power consum ption can now be calculated for these conditions by adding a typical internal power dissipation: p total = p ext + (i ddin 2 5.0 v) note that the conditions causing a worst-case p ext are different from those causing a worst-case p int . maximum p int cannot occur while 100% of the output pi ns are switching from all ones to all zeros. note also that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously. table 5. external power calculations (5 v devices) pin type no. of pins % switching c f v dd 2 = p ext address 15 50 44.7 pf 10 mhz 25 v = 0.084 w ms0 10 44.7 pf 10 mhz 25 v = 0.000 w wr 1C 44.7 pf 20 mhz 25 v = 0.022 w data 32 50 14.7 pf 10 mhz 25 v = 0.059 w addrclk 1 C 4.7 pf 20 mhz 25 v = 0.002 w p ext = 0.167 w
rev. g | page 18 of 64 | august 2010 adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc adsp-21060l/adsp-2106 2l specifications note that component specificat ions are subject to change without notice. operating conditions (3.3 v) electrical characteristics (3.3 v) a grade c grade k grade parameter description min max min max min max unit v dd supply voltage 3.15 3.45 3.15 3.45 3.15 3.45 v t case case operating temperature C40 +85 C40 +100 C40 +85 c v ih 1 1 1 applies to input and bidirectional pins: da ta47C0, addr31C0, rd , wr , sw , ack, sbts , irq2C0 , flag3C0, hgb , cs , dmar1 , dmar2 , br6C1 , id2C0, rpba, cpa , tfs0, tfs1, rfs0, rfs1, lxdat3C0, lxclk, lxack, eboot, lboot, bms , tms, tdi, tck, hbr , dr0, dr1, tclk0, tclk1, rclk0, rclk1 high level input voltage @ v dd = max 2.0 v dd + 0.5 2.0 v dd + 0.5 2.0 v dd + 0.5 v v ih 2 2 2 applies to input pins: clkin, reset , trst high level input voltage @ v dd = max 2.2 v dd + 0.5 2.2 v dd + 0.5 2.2 v dd + 0.5 v v il 1, 2 low level input voltage @ v dd = min C0.5 +0.8 C0.5 +0.8 C0.5 +0.8 v parameter description test conditions min max unit v oh 1, 2 high level output voltage @ v dd = min, i oh = C2.0 ma 2.4 v v ol 1, 2 low level output voltage @ v dd = min, i ol = 4.0 ma 0.4 v i ih 3, 4 high level input current @ v dd = max, v in = v dd max 10 a i il 3 low level input current @ v dd = max, v in = 0 v 10 a i ilp 4 low level input current @ v dd = max, v in = 0 v 150 a i ozh 5, 6, 7, 8 three-state leakage current @ v dd = max, v in = v dd max 10 a i ozl 5, 9 three-state leakage current @ v dd = max, v in = 0 v 10 a i ozhp 9 three-state leakage current @ v dd = max, v in = v dd max 350 a i ozlc 7 three-state leakage current @ v dd = max, v in = 0 v 1.5 ma i ozla 10 three-state leakage current @ v dd = max, v in = 1.5 v 350 a i ozlar 8 three-state leakage current @ v dd = max, v in = 0 v 4.2 ma i ozls 6 three-state leakage current @ v dd = max, v in = 0 v 150 a c in 11, 12 input capacitance f in = 1 mhz, t case = 25c, v in = 2.5 v 4.7 pf 1 applies to output and bidirectional pins: da ta47C0, addr31C0, ms3C0 , rd , wr , page, adrclk, sw , ack, flag3C0, timexp, hbg , redy, dmag1 , dmag2 , br6C1 , cpa, dt0, dt1, tclk0, tclk1, rclk0, rclk1, tfs0, tfs1, rfs0, rfs1, lxdat3C0, lxclk, lxack, bms , tdo, emu , icsa. 2 see output drive currents for ty pical drive current capabilities. 3 applies to input pins: ack, sbts , irq2 C0 , hbr , cs , dmar1 , dmar2 , id2C0, rpba, eboot, lboot, clkin, reset , tck. 4 applies to input pins with internal pull-ups: dr0, dr1, trst , tms, tdi. 5 applies to three-statable pin s: data47C0, addr31C0, ms3C0 , rd , wr , page, adrclk, sw , ack, flag3C0, hbg , redy, dmag1 , dmag2 , bms , br6C1 , tfsx, rfsx, tdo, emu . (note that ack is pulled up internally with 2 k during reset in a multiprocessor system, when id2C0 = 001 and another adsp-2106x is not requesting bus mastership.) 6 applies to three-statable pins with internal pu ll-ups: dt0, dt1, tclk0, tclk1, rclk0, rclk1. 7 applies to cpa pin. 8 applies to ack pin when pulled up. (note th at ack is pulled up internally with 2 k during reset in a multiproc essor system, when id2C0 = 001 and another adsp-2106xl is not requesting bus mastership). 9 applies to three-statable pins with inte rnal pull-downs: lxdat3C0, lxclk, lxack. 10 applies to ack pin when keeper latch enabled. 11 applies to all signal pins. 12 guaranteed but not tested.
adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc rev. g | page 19 of 64 | august 2010 internal power dissipation (3.3 v) these specifications apply to th e internal power portion of v dd only. for a complete discussion of the code used to measure power dissipation, see the technical note sharc power dissi- pation measurements. specifications are based on the operating scenarios. to estimate power consumption fo r a specific application, use the following equation where % is the amount of time your pro- gram spends in that state: %peak i ddinpeak + %high i ddinhigh + %low i ddinlow + %idle i ddidle = power consumption operation peak activity (i ddinpeak ) high activity (i ddinhigh ) low activity (i ddinlow ) instruction type multifunction multifunction single function instruction fetch cache internal memory internal memory core memory access 2 per cycle (dm and pm) 1 per cycle (dm) none internal memory dma 1 per cycle 1 per 2 cycles 1 per 2 cycles parameter test conditions max units i ddinpeak supply current (internal) 1 t ck = 30 ns, v dd = max t ck = 25 ns, v dd = max 540 600 ma ma i ddinhigh supply current (internal) 2 t ck = 30 ns, v dd = max t ck = 25 ns, v dd = max 425 475 ma ma i ddinlow supply current (internal) 2 t ck = 30 ns, v dd = max t ck = 25 ns, v dd = max 250 275 ma ma i ddidle supply current (idle) 3 v dd = max 180 ma 1 the test program used to measure i ddinpeak represents worst case processor operation and is not sustaina ble under normal application co nditions. actual internal power measurements made using typical appl ications are less than specified. 2 i ddinhigh is a composite average based on a range of high activity code. i ddinlow is a composite avera ge based on a range of low activity code. 3 idle denotes adsp-2106xl state duri ng execution of idle instruction.
rev. g | page 20 of 64 | august 2010 adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc external power dissipation (3.3 v) total power dissipation has two components, one due to inter- nal circuitry and one due to the switching of external output drivers. internal power dissipation is dependent on the instruc- tion execution sequence and the data operands involved. internal power dissipation is calculated in the following way: p int = i ddin v dd the external component of total power dissipation is caused by the switching of output pins. its magnitude depends on: ? the number of output pins th at switch during each cycle (o) ? the maximum frequency at which they can switch (f) ? their load capacitance (c) ? their voltage swing (v dd ) and is calculated by: p ext = o c v dd 2 f the load capacitance should in clude the processors package capacitance (cin). the switchin g frequency includes driving the load high and then back low. address and data pins can drive high and low at a maximum rate of 1/(2t ck ). the write strobe can switch every cycle at a frequency of 1/t ck . select pins switch at 1/(2t ck ), but selects can switch on each cycle. example: estimate p ext with the following assumptions: ? a system with one bank of external data memory ram (32-bit) ? four 128k 8 ram chips are used, each with a load of 10 pf ? external data memory writes occur every other cycle, a rate of 1/(4t ck ), with 50% of the pins switching ? the instruction cycl e rate is 40 mhz (t ck = 25 ns) the p ext equation is calculated for each class of pins that can drive: a typical power consumption can now be calculated for these conditions by adding a typical internal power dissipation: p total = p ext + (i ddin 2 5.0 v) note that the conditions causing a worst-case p ext are different from those causing a worst-case p int . maximum p int cannot occur while 100% of the output pi ns are switching from all ones to all zeros. note also that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously. absolute maximum ratings stresses greater than those listed table 7 may cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specifica- tion is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 6. external power calculations (3.3 v devices) pin type no. of pins % switching c f v dd 2 = p ext address 15 50 44.7 pf 10 mhz 10.9 v = 0.037 w ms0 10 44.7 pf 10 mhz 10.9 v = 0.000 w wr 1C 44.7 pf 20 mhz 10.9 v = 0.010 w data 32 50 14.7 pf 10 mhz 10.9 v = 0.026 w addrclk 1 C 4.7 pf 20 mhz 10.9 v = 0.001 w p ext = 0.074 w table 7. absolute maximum ratings parameter adsp-21060/adsp-21060c adsp-21062 adsp-21060l/adsp-21060lc adsp-21062l 5 v 3.3 v supply voltage (v dd ) C0.3 v to +7.0 v C0.3 v to +4.6 v input voltage C0.5 v to v dd + 0.5 v C0.5 v to v dd +0.5 v output voltage swing C0.5 v to v dd + 0.5 v C0.5 v to v dd + 0.5 v load capacitance 200 pf 200 pf storage temperature range C65 c to +150 cC65 c to +150 c lead temperature (5 seconds) 280 c2 8 0 c junction temperature under bias 130 c1 3 0 c
adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc rev. g | page 21 of 64 | august 2010 esd caution package marking information figure 8 and table 8 provide information on detail contained within the package marking fo r the adsp-2106x processors (actual marking format may vary ). for a complete listing of product availability, see ordering guide on page 62 . timing specifications the adsp-2106x processors are available at maximum proces- sor speeds of 33 mhz (C133), and 40 mhz (C160). the timing specifications are based on a clkin frequency of 40 mhz t ck = 25 ns). the dt derating factor enables the calculation for timing specifications within the min to max range of the t ck specification (see table 9 ). dt is the difference between the derated clkin period and a clkin period of 25 ns: dt = t ck C 25 ns use the exact timing information given. do not attempt to derive parameters from the addition or subtraction of others. while addition or subtraction would yield meaningful results for an individual device, the va lues given in this data sheet reflect statistical variations and worst cases. consequently, you cannot meaningfully add parame ters to derive longer times. for voltage reference levels, see figure 28 on page 48 under test conditions. timing requirements apply to signals that are controlled by cir- cuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the processor operates correctly with other devices. (o/d) = open drain, (a/d) = active drive. switching characteristics specify how the processor changes its signals. you have no control over this timingcircuitry external to the processor must be designed for compatibility with these signal characteristics. switching characteristics tell you what the processor will do in a given ci rcumstance. you can also use switching characteristics to ensu re that any timing requirement of a device connected to the processor (such as memory) is satisfied. figure 8. typical package brand table 8. package brand information brand key field description t temperature range pp package type z lead (pb) free option ccc see ordering guide vvvvvv.x assembly lot code n.n silicon revision yyww date code esd (el ectrostatic discharge) sensitive device. charged devic es and c irc uit boards c an disc harge without detection. although this product features patented or proprietary protec tion c irc uitry, damage may o ccur on devic es subj e c ted to high energy esd. t herefore, proper esd prec autions shoul d be taken to avoid performanc e degradation or loss of functionality. vvvvvv.x n.n tppzccc s adsp-2106x a yyww country_of_origin
rev. g | page 22 of 64 | august 2010 adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc clock input reset table 9. clock input parameter adsp-21060 adsp-21062 40 mhz, 5 v adsp-21060 adsp-21062 33 mhz, 5 v adsp-21060l adsp-21062l 40 mhz, 3.3 v adsp-21060l adsp-21062l 33 mhz, 3.3 v unit minmaxminmaxminmaxminmax timing requirements t ck clkin period 25 100 30 100 25 100 30 100 ns t ckl clkin width low 7 7 8.75 8.75 1 ns t ckh c l k i n w i d t h h i g h5555n s t ckrf clkin rise/fall (0.4 v to 2.0 v) 3 3 3 3 ns 1 for the adsp-21060lc, this sp ecification is 9.5 ns min. figure 9. clock input cli t ch t cl t c table 10. reset 5 v and 3.3 v unit parameter min max timing requirements t wrst reset pulse width low 1 4t ck ns t srst reset setup before clkin high 2 14 + dt/2 t ck ns 1 applies after the power-up sequence is comp lete. at power-up, the proces sors internal phase-locked l oop requires no more than 1 00 s while reset is low, assuming stable v dd and clkin (not including start-up time of external clock oscillator). 2 only required if multiple adsp-210 6xs must come out of reset synchronous to clkin with program counters (pc) equal. not require d for multiple ad sp-2106xs commu- nicating over the shared bus (through th e external port), because the bus arbitration logic automatically synchronizes itself a fter reset. figure 10. reset cli reset wr s s s
adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc rev. g | page 23 of 64 | august 2010 interrupts timer table 11. interrupts 5 v and 3.3 v unit parameter min max timing requirements t sir irq2C0 setup before clkin high 1 18 + 3dt/4 ns t hir irq2C0 hold before clkin high 1 12 + 3dt/4 ns t ipw irq2C0 pulse width 2 2+t ck ns 1 only required for irqx recognition in the following cycle. 2 applies only if t sir and t hir requirements are not met. figure 11. interrupts cli irq20 t ipw t s table 12. timer 5 v and 3.3 v unit parameter min max switching characteristic t dtex clkin high to timexp 15 ns figure 12. timer cli timep t dte t dte
rev. g | page 24 of 64 | august 2010 adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc flags table 13. flags 5 v and 3.3 v unit parameter min max timing requirements t sfi flag3C0 in setup before clkin high 1 8 + 5dt/16 ns t hfi flag3C0 in hold after clkin high 1 0 C 5dt/16 ns t dwrfi flag3C0 in delay after rd /wr low 1 5 + 7dt/16 ns t hfiwr flag3C0 in hold after rd /wr deasserted 1 0n s switching characteristics t dfo flag3C0 out delay after clkin high 16 ns t hfo flag3C0 out hold after clkin high 4 ns t dfoe clkin high to flag3C0 out enable 3 ns t dfod clkin high to flag3C0 out disable 14 ns 1 flag inputs meeting these setup and hold times for instruction cycle n will affect conditional instructions in instruction cycl e n+2. figure 13. flags cli flag 3 s rd wr flag 3
adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc rev. g | page 25 of 64 | august 2010 memory readbus master use these specifications for asyn chronous interfacing to memo- ries (and memory-mapped periph erals) without reference to clkin. these specifications apply when the adsp-2106x is the bus master accessing external memory space in asynchronous access mode. note that timing for ack, data, rd , wr , and dmagx strobe timing parameters only applies to asynchronous access mode. table 14. memory readbus master 5 v and 3.3 v unit parameter min max timing requirements t dad address selects delay to data valid 1, 2 18 + dt+w ns t drld rd low to data valid 1 12 + 5dt/8 + w ns t hda data hold from address, selects 3 0.5 ns t hdrh data hold from rd high 3 2.0 ns t daak ack delay from address, selects 2, 4 14 + 7dt/8 + w ns t dsak ack delay from rd low 4 8 + dt/2 + w ns switching characteristics t drha address selects hold after rd high 0+h ns t darl address selects to rd low 2 2 + 3dt/8 ns t rw rd pulse width 12.5 + 5dt/8 + w ns t rwr rd high to wr , rd , dmagx low 8 + 3dt/8 + hi ns t sadadc address, selects setup before adrclk high 2 0 + dt/4 ns w = (number of wait states specified in wait register) t ck . hi = t ck (if an address hold cycle or bus idle cycle occurs , as specified in wait register; otherwise hi = 0). h = t ck (if an address hold cycle occurs as specified in wait register; otherwise h = 0). 1 data delay/setup: user must meet t dad or t drld or synchronous spec t ssdati . 2 the falling edge of msx , sw , bms is referenced. 3 data hold: user must meet t hda or t hdrh or synchronous spec t hsdati . see example system hold time calculation on page 48 for the calculation of ho ld times given capacitive and dc loads. 4 ack is not sampled on external memory accesse s that use the internal wait state mode. for the first clkin cycle of a new extern al memory access, ack must be valid by t daak or t dsak or synchronous specification t sackc for wait state modes external, either, or both (both, if the internal wait state is zero). for the second and subsequent cycle s of a wait stated external memory a ccess, synchronous specifications t sackc and t hack must be met for wait state modes external, either, or both (both, after internal wait states have completed). figure 14. memory readbus master wr , dmag ack data rd addre ss s , sw bms t darl t rw t dad t s adadc t daak t hdrh t hda t rwr t drld adrclk (out) t drha t d s ak
rev. g | page 26 of 64 | august 2010 adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc memory writebus master use these specifications for asyn chronous interfacing to memo- ries (and memory-mapped periph erals) without reference to clkin. these specifications a pply when the adsp-2106x is the bus master accessing external memory space in asynchronous access mode. note that timing for ack, data, rd , wr , and dmagx strobe timing parameters only applies to asynchronous access mode. table 15. memory writebus master 5 v and 3.3 v unit parameter min max timing requirements t daak ack delay from address, selects 1, 2 14 + 7dt/8 + w ns t dsak ack delay from wr low 1 8 + dt/2 + w ns switching characteristics t dawh address selects to wr deasserted 2 17 + 15dt/16 + w ns t dawl address selects to wr low 2 3 + 3dt/8 ns t ww wr pulse width 12 + 9dt/16 + w ns t ddwh data setup before wr high 7 + dt/2 + w ns t dwha address hold after wr deasserted 0.5 + dt/16 + h ns t datrwh data disable after wr deasserted 3 1 + dt/16 +h 6 + dt/16+h ns t wwr wr high to wr , rd , dmagx low 8 + 7dt/16 + h ns t ddwr data disable before wr or rd low 5 + 3dt/8 + i ns t wde wr low to data enabled C1 + dt/16 ns t sadadc address, selects setup before adrclk high 2 0 + dt/4 ns w = (number of wait states specified in wait register) t ck . h = t ck (if an address hold cycle occurs, as specified in wait register; otherwise h = 0). hi = t ck (if an address hold cycle or bus idle cycle occurs , as specified in wait register; otherwise hi = 0). i = t ck (if a bus idle cycle occurs, as specified in wait register; otherwise i = 0). 1 ack is not sampled on external memory accesse s that use the internal wait state mode. for the first clkin cycle of a new extern al memory access, ack must be valid by t daak or t dsak or synchronous specification t sackc for wait state modes external, either, or both (both, if the internal wait state is zero). for the second and subsequent cycle s of a wait stated external memory a ccess, synchronous specifications t sackc and t hack must be met for wait state modes external, either, or both (both, after internal wait states have completed). 2 the falling edge of msx , sw , bms is referenced. 3 see example system hold time calculation on page 48 for calculation of hold times given capacitive and dc loads.
adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc rev. g | page 27 of 64 | august 2010 figure 15. memory writebus master rd , dmag ack data wr addre ss msx , sw bms t ww t s adadc t daak t wwr adrclk (out) t dwha t d s ak t dawl t wde t ddwr t datrwh t ddwh t dawh
rev. g | page 28 of 64 | august 2010 adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc synchronous read/writebus master use these specifications for interfacing to external memory sys- tems that require clkinrelative timing or for accessing a slave adsp-2106x (in multiprocessor memory space). these synchronous switching characteri stics are also valid during asynchronous memory reads and writes except where noted (see memory readbus ma ster on page 25 and memory write bus master on page 26 ). when accessing a slave adsp-2106x, these switching characteristics must meet the slaves timing requirements for synchronous read/writes (see synchronous read/writebus slave on page 30 ). the slave adsp-2106x must also meet these (bus master ) timing requirements for data and acknowledge setup and hold times. table 16. synchronous read/writebus master 5 v and 3.3 v unit parameter min max timing requirements t ssdati data setup before clkin 3 + dt/8 ns t hsdati data hold after clkin 3.5 C dt/8 ns t daak ack delay after address, selects 1, 2 14 + 7dt/8 + w ns t sackc ack setup before clkin 2 6.5+dt/4 ns t hack ack hold after clkin C1 C dt/4 ns switching characteristics t dadro address, msx , bms , sw delay after clkin 1 7 C dt/8 ns t hadro address, msx , bms , sw hold after clkin C1 C dt/8 ns t dpgc page delay after clkin 9 + dt/8 16 + dt/8 ns t drdo rd high delay after clkin C2 C dt/8 4 C dt/8 ns t dwro wr high delay after clkin C3 C 3dt/16 4 C 3dt/16 ns t drwl rd /wr low delay after clkin 8 + dt/4 12.5 + dt/4 ns t sddato data delay after clkin 19 + 5dt/16 ns t dattr data disable after clkin 3 0 C dt/8 7 C dt/8 ns t dadcck adrclk delay after clkin 4 + dt/8 10 + dt/8 ns t adrck adrclk period t ck ns t adrckh adrclk width high (t ck /2 C 2) ns t adrckl adrclk width low (t ck /2 C 2) ns 1 the falling edge of msx , sw , bms is referenced. 2 ack delay/setup: user must meet t daak or t dsak or synchronous specification t sakc for deassertion of ack (low), all three spec ifications must be met for assertion of ack (high). 3 see example system hold time calculation on page 48 for calculation of hold times given capacitive and dc loads.
adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc rev. g | page 29 of 64 | august 2010 figure 16. synchronous read/writebus master clkin addrclk addre ss , bms , sw , msx ack (in) page rd data (out) wr data (in) write cycle read cycle t drwl t h s dati t ss dati t drdo t dwro t dattr t s ddato t drwl t dadcck t adrck t adrckl t hadro t dpgc t s ackc t hack t dadro t adrckh t daak
rev. g | page 30 of 64 | august 2010 adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc synchronous read/writebus slave use these specifications for bus master accesses of a slaves iop registers or internal memory (i n multiprocessor memory space). the bus master must meet the bus slave timing requirements. table 17. synchronous read/writebus slave 5 v and 3.3 v unit parameter min max timing requirements t sadri address, sw setup before clkin 15 + dt/2 ns t hadri address, sw hold after clkin 5 + dt/2 ns t srwli rd /wr low setup before clkin 1 9.5 + 5dt/16 ns t hrwli rd /wr low hold after clkin 2 C4 C 5dt/16 8 + 7dt/16 ns t rwhpi rd /wr pulse high 3 ns t sdatwh data setup before wr high 5 ns t hdatwh data hold after wr high 1 ns switching characteristics t sddato data delay after clkin 3 18 + 5dt/16 ns t dattr data disable after clkin 4 0 C dt/8 7 C dt/8 ns t dackad ack delay after address, sw 5 9n s t acktr ack disable after clkin 5 C1 C dt/8 6 C dt/8 ns 1 t srwli (min) = 9.5 + 5dt/16 when mult iprocessor memory space wait state (mmsws bit in wait register) is disabled; when mmsws is enabl ed, t srwli (min)= 4 + dt/8. 2 for adsp-21060c specific ation is C3.5 C 5dt/16 ns min, 8 + 7dt/16 ns max; for adsp-21060lc specification is C3.75 C 5dt/16 ns m in, 8 + 7dt/16 ns max. 3 for adsp-21062/adsp-21062 l/adsp-21060c specific ation is 19 + 5dt/16 ns ma x; for adsp-21060lc specifi cation is 19.25 + 5dt/16 ns max. 4 see example system hold time calculation on page 48 for calculation of hold times given capacitive and dc loads. 5 t dackad is true only if the address and sw inputs have setup times (before clkin) grea ter than 10 + dt/8 and less than 19 + 3dt/4. if the address and inputs have setup t imes greater than 19 + 3dt/4, then ack is valid 14 + dt/4 (max) after clkin. a slave that sees an address with an m field match will respond with ack regardless of the state of mmsws or strobes. a slave will three-state ack every cycle with t acktr . figure 17. synchronous read/writebus slave cli addre ss rd data (out wr write acce ss ss s s s s s
adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc rev. g | page 31 of 64 | august 2010 multiprocessor bus request and host bus request use these specifications for passi ng of bus mastership between multiprocessing adsp-2106xs (brx ) or a host processor, both synchronous and asynchronous (hbr , hbg ). table 18. multiprocessor bus request and host bus request 5 v and 3.3 v unit parameter min max timing requirements t hbgrcsv hbg low to rd /wr /cs valid 1 20 + 5dt/4 ns t shbri hbr setup before clkin 2 20 + 3dt/4 ns t hhbri hbr hold after clkin 2 14 + 3dt/4 ns t shbgi hbg setup before clkin 13 + dt/2 ns t hhbgi hbg hold after clkin high 6 + dt/2 ns t sbri brx , cpa setup before clkin 3 13 + dt/2 ns t hbri brx , cpa hold after clkin high 6 + dt/2 ns t srpbai rpba setup before clkin 21 + 3dt/4 ns t hrpbai rpba hold after clkin 12 + 3dt/4 ns switching characteristics t dhbgo hbg delay after clkin 7 C dt/8 ns t hhbgo hbg hold after clkin C2 C dt/8 ns t dbro brx delay after clkin 7 C dt/8 ns t hbro brx hold after clkin C2 C dt/8 ns t dcpao cpa low delay after clkin 4 8 C dt/8 ns t trcpa cpa disable after clkin C2 C dt/8 4.5 C dt/8 ns t drdycs redy (o/d) or (a/d) low from cs and hbr low 5, 6 8.5 ns t trdyhg redy (o/d) disable or redy (a/d) high from hbg 6, 7 44 + 23dt/16 ns t ardytr redy (a/d) disable from cs or hbr high 6 10 ns 1 for first asynchronous access after hbr and cs asserted, addr31-0 must be a non-mms value 1/2 t ck before rd or wr goes low or by t hbgrcsv after hbg goes low. this is easily accomplished by driving an upper address signal high when hbg is asserted. see the host processor control of the adsp-2106x section in the adsp-2106x sharc users manual, revision 2.1. 2 only required for recognition in the current cycle. 3 cpa assertion must meet the setup to clkin; deassert ion does not need to meet the setup to clkin. 4 for adsp-21060lc, specificat ion is 8.5 C dt/8 ns max. 5 for adsp-21060l, specification is 9.5 ns max, for adsp-21060lc, specification is 11.0 ns max, for adsp-210 62l, specification is 8.75 ns max. 6 (o/d) = open drain, (a/d) = active drive. 7 for adsp-21060c/adsp-21060lc, specif ication is 40 + 23dt/16 ns min.
rev. g | page 32 of 64 | august 2010 adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc figure 18. multiprocessor bus request and host bus request b rx , cpa ( in, o/ d) hbr cs rp ba re d y (o /d ) redy (a /d ) hbg (out) rd wr cs o/d = open drain, a/d = active drive t s rpbai hb g (i n) clkin hbr hbg (out) brx (out) cpa (out, o/d) t hhbgo t hbro t trcp a t hrpbai t hbri t s bri t s hbgi t hhbgi t dcpao t dbro t dhbgo t hhbri t s hbri t drdyc s t trdyhg t hbgrc s v t ardytr
adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc rev. g | page 33 of 64 | august 2010 asynchronous read/writehost to adsp-2106x use these specifications for asynchronous host processor accesses of an adsp-2106x, afte r the host has asserted cs and hbr (low). after hbg is returned by the adsp-2106x, the host can drive the rd and wr pins to access the adsp-2106xs internal memory or iop registers. hbr and hbg are assumed low for this timing. not required if and address are valid t hbgrcsv after goes low. for first acce ss after asserted, addr31C0 must be a non-mms value 1/2 t clk before or goes low or by t hbgrcsv after goes low. this is easily accomplished by driving an upper address signal high when is a sserted. see the host processor control of the adsp-2106x section in the adsp-2106x sharc users manual , revision 2.1. table 19. read cycle 5 v and 3.3 v unit parameter min max timing requirements t sadrdl address setup/cs low before rd low 1 0n s t hadrdh address hold/cs hold low after rd 0n s t wrwh rd /wr high width 6 ns t drdhrdy rd high delay after redy (o/d) disable 0 ns t drdhrdy rd high delay after redy (a/d) disable 0 ns switching characteristics t sdatrdy data valid before redy disable from low 2 ns t drdyrdl redy (o/d) or (a/d) low delay after rd low 2 10 ns t rdyprd redy (o/d) or (a/d) low pulse width for read 45 + 21dt/16 ns t hdarwh data disable after rd high 3 28n s 1 not required if rd and address are valid t hbgrcsv after hbg goes low. for first access after hbr asserted, addr31-0 must be a non-mms value 1/2 t clk before rd or wr goes low or by t hbgrcsv after hbg goes low. this is easily acc omplished by driving an upper address signal high when hbg is asserted. see the host processor control of the adsp-2106x section in the adsp-2106x sharc users manual, revision 2.1. 2 for adsp-21060l, specification is 10.5 ns max; for adsp-21060lc, specification is 12.5 ns max. 3 for adsp-21060l/adsp-21060lc, specif ication is 2 ns min, 8.5 ns max. table 20. write cycle 5 v and 3.3 v unit parameter min max timing requirements t scswrl cs low setup before wr low 0 ns t hcswrh cs low hold after wr high 0 ns t sadwrh address setup before wr high 5 ns t hadwrh address hold after wr high 2 ns t wwrl wr low width 7 ns t wrwh rd /wr high width 6 ns t dwrhrdy wr high delay after redy (o/d) or (a/d) disable 0 ns t sdatwh data setup before wr high 5 ns t hdatwh data hold after wr high 1 ns switching characteristics t drdywrl redy (o/d) or (a/d) low delay after wr /cs low 10 ns t rdypwr redy (o/d) or (a/d) low pulse width for write 15 + 7dt/16 ns t srdyck redy (o/d) or (a/d) disable to clkin 1 + 7dt/16 8 + 7dt/16 ns
rev. g | page 34 of 64 | august 2010 adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc figure 19. synchronous redy timing figure 20. asynchronous read/writehost to adsp-2106x clkin re dy ( o/d ) o/d = open drain, a/d = active drive t s rdyck red y (a /d ) t s adrdl redy (o/d ) rd t dr dy r dl t wrwh t hadrdh t hdarwh t r d ypr d t drdhrdy t s datrdy read cycle addre ss / cs da t a ( ou t ) redy (a/d) o/d = open drain, a/d = active drive t s da t w h t hdatwh t wwrl re d y ( o/d ) wr t drdywrl t wrwh t hadwrh t rdypwr t dwrhrdy write cycle t s adwrh data (in) addre ss redy (a/d) t s c s wrl cs t hc s wrh
adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc rev. g | page 35 of 64 | august 2010 three-state timingbus master, bus slave these specifications show how the memory interface is disabled (stops driving) or enabled (resum es driving) relative to clkin and the sbts pin. this timing is applic able to bus master transi- tion cycles (btc) and host transi tion cycles (htc) as well as the sbts pin. table 21. three-state timing bus master, bus slave 5 v and 3.3 v unit parameter min max timing requirements t stsck sbts setup before clkin 12 + dt/2 ns t htsck sbts hold before clkin 6 + dt/2 ns switching characteristics t miena address/select enable after clkin 1 C1.5 C dt/8 ns t miens strobes enable after clkin 2 C1.5 C dt/8 ns t mienhg hbg enable after clkin C1.5 C dt/8 ns t mitra address/select disable after clkin 3 0 C dt/4 ns t mitrs strobes disable after clkin 2 1.5 C dt/4 ns t mitrhg hbg disable after clkin 2.0 C dt/4 ns t daten data enable after clkin 4 9 + 5dt/16 ns t dattr data disable after clkin 4 0 C dt/8 7 C dt/8 ns t acken ack enable after clkin 4 7.5 + dt/4 ns t acktr ack disable after clkin 4 C1 C dt/8 6 C dt/8 ns t adcen adrclk enable after clkin C2 C dt/8 ns t adctr adrclk disable after clkin 8 C dt/4 ns t mtrhbg memory interface disable before hbg low 5 0 + dt/8 ns t menhbg memory interface enable after hbg high 5 19 + dt ns 1 for adsp-21060l/adsp-21060lc/adsp- 21062l, specification is C1.25 C dt/8 ns min, fo r adsp-21062, specificatio n is C1 C dt/8 ns m in. 2 strobes = rd , wr , page, dmag , bms , sw . 3 for adsp-21060lc, specificatio n is 0.25 C dt/4 ns max. 4 in addition to bus master transition cycles, these specs al so apply to bus master and bus slave synchronous read/write. 5 memory interface = address, rd , wr , msx , sw , page, dmagx , and bms (in eprom boot mode). figure 21. three-state timing (bus transition cycle, sbts assertion) memory iterface hbg memor iterface addre ss rd, wr , msx , sw ,page, dmagx. bms (i eprom boot mode mehbg mtrhbg
rev. g | page 36 of 64 | august 2010 adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc figure 22. three-state timing (bus transition cycle, sbts assertion) clkin sbts ack adrclk data memory interface t mitra, t mitr s , t mitrhg t s t s ck t ht s ck t dattr t daten t acktr t acken t adctr t adcen t miena, t mien s , t mienhg
adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc rev. g | page 37 of 64 | august 2010 dma handshake these specifications describe the three dma handshake modes. in all three modes, dmarx is used to initiate transfers. for handshake mode, dmagx controls the latchi ng or enabling of data externally. for external handshake mode, the data transfer is controlled by the addr31C0, rd , wr , page, ms3C0 , ack, and dmag x signals. for paced master mode, the data transfer is controlled by addr31C0, rd , wr , ms3C0 , and ack (not dmag ). for paced master mode, the memory read-bus mas- ter, memory write-bus master , and synchronous read/write- bus master timing specifications for addr31C0, rd , wr , ms3C0 , page, data63C0, and ack also apply. table 22. dma handshake 5 v and 3.3 v unit parameter min max timing requirements t sdrlc dmarx low setup before clkin 1 5n s t sdrhc dmarx high setup before clkin 1 5n s t wdr dmarx width low (nonsynchronous) 6 ns t sdatdgl data setup after dmagx low 2 10 + 5dt/8 ns t hdatidg data hold after dmagx high 2 ns t datdrh data valid after dmarx high 2 16 + 7dt/8 ns t dmarll dmarx low edge to low edge 23 + 7dt/8 ns t dmarh dmarx width high 2 6n s switching characteristics t ddgl dmagx low delay after clkin 9 + dt/4 15 + dt/4 ns t wdgh dmagx high width 6 + 3dt/8 ns t wdgl dmagx low width 12 + 5dt/8 ns t hdgc dmagx high delay after clkin C2 C dt/8 6 C dt/8 ns t vdatdgh data valid before dmagx high 3 8 + 9dt/16 ns t datrdgh data disable after dmagx high 4 07n s t dgwrl wr low before dmagx low 5 02n s t dgwrh dmag x low before wr high 10 + 5dt/8 +w ns t dgwrr wr high before dmagx high 1 + dt/16 3 + dt/16 ns t dgrdl rd low before dmagx low 0 2 ns t drdgh rd low before dmagx high 11 + 9dt/16 + w ns t dgrdr rd high before dmagx high 0 3 ns t dgwr dmagx high to wr , rd , dmagx low 5 + 3dt/8 + hi ns t dadgh address/select valid to dmagx high 17 + dt ns t ddgha address/select hold after dmagx high 6 C0.5 ns w = (number of wait states specified in wait register) t ck . hi = t ck (if data bus idle cycle occurs, as specified in wait register; otherwise hi = 0). 1 only required for recognition in the current cycle. 2 t sdatdgl is the data setup requirement if dmarx is not being used to hold off compl etion of a write. otherwise, if dmarx low holds off completion of the write, the data can be driven t datdrh after dmarx is brought high. 3 t vdatdgh is valid if dmarx is not being used to hold off completion of a read. if dmarx is used to prolong the read, then t vdatdgh =t ck C0.25t cclk C8+(nt ck ) where n equals the number of extra cycles that the access is prolonged. 4 see example system hold time calculation on page 48 for calculation of hold times given capacitive and dc loads. 5 for adsp-21062/adsp-21062l specificat ion is C2.5 ns min, 2 ns max. 6 for adsp-21060l/adsp-21062l sp ecification is C1 ns min.
rev. g | page 38 of 64 | august 2010 adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc figure 23. dma handshake clkin t s drlc dmarx data (out) data (in) rd wr t wdr t s drhc t dmarh t dmarll t hdgc t wdgh t ddgl dmagx t vdatdgh t datdrh t datrdgh t hdatidg t dgwrl t dgwrh t dgwrr t dgrdl t drdgh t dgrdr t s datdgl *memory read bu s ma s ter, memory write bu s ma s ter, or s ynchronou s read/write bu s ma s ter timing s pecification s for addr 3 1C0, rd , wr , sw ms3C0 , and ack al s o apply here. (external device to external memory) (external memory to external device) trans fer s between ad s p-2106x internal memory and external device tran s fer s between external device and external memory* (external hand s hake mode) t ddgha addr ms x, sw t dadgh t wdgl (from external device to ad s p-2106x) (from ad s p-2106x to external device)
adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc rev. g | page 39 of 64 | august 2010 link ports 1 clk speed operation table 23. link portsreceive 5 v 3.3 v unit parameter min max min max timing requirements t sldcl data setup before lclk low 1 3.5 3 ns t hldcl data hold after lclk low 3 3 ns t lclkiw lclk period (1 operation) t ck t ck ns t lclkrwl lclk width low 6 6 ns t lclkrwh l c l k w i d t h h i g h 55n s switching characteristics t dlahc lack high delay after clkin high 2, 3 18 + dt/2 28.5 + dt/2 18 + dt/2 28.5 + dt/2 ns t dlalc lack low delay after lclk high C3 +13 C3 +13 ns t endlk lack enable from clkin 5 + dt/2 5 + dt/2 ns t tdlk lack disable from clkin 20 + dt/2 20 + dt/2 ns 1 for adsp-21062, specification is 3 ns min. 2 lack goes low with t dlalc relative to rise of lclk af ter first nibble, but does not go low if the receivers link buffer is not about to fill. 3 for adsp-21060c, specification is 18 + dt/2 ns min, 29 + dt/2 ns max. table 24. link portstransmit 5 v 3.3 v unit parameter min max min max timing requirements t slach lack setup before lclk high 1 18 18 ns t hlach lack hold after lclk high C7 C7 ns switching characteristics t dlclk data delay after clkin (1 operation) 2 15.5 15.5 ns t dldch data delay after lclk high 3 32 . 5 n s t hldch data hold after lclk high C3 C3 ns t lclktwl lclk width low 4 (t ck /2) C 2 (t ck /2) + 2 (t ck /2) C 1 (t ck /2) + 1.25 ns t lclktwh lclk width high 5 (t ck /2) C 2 (t ck /2) + 2 (t ck /2) C 1.25 (t ck /2) + 1 ns t dlaclk lclk low delay after lack high 6 (t ck /2) + 8.5 (3 t ck /2) + 17 (t ck /2) + 8 (3 t ck /2) + 17.5 ns t endlk lack enable from clkin 5 + dt/2 5 + dt/2 ns t tdlk lack disable from clkin 20 + dt/2 20 + dt/2 ns 1 for adsp-21060l/adsp-21060lc, specification is 20 ns min. 2 for adsp-21060l, specification is 16.5 ns max; for adsp-21060lc, specification is 16.75 ns max. 3 for adsp-21062, specific ation is 2.5 ns max. 4 for adsp-21062, specification is (t ck /2) C 1 ns min, (t ck /2) + 1.25 ns max; for adsp -21062l, specification is (t ck /2) C 1 ns min, (t ck /2) + 1.5 ns max; for adsp-21060lc specification is (t ck /2) C 1 ns min, (t ck /2) + 2.25 ns max. 5 for adsp-21062, specification is (t ck /2) C 1.25 ns min, (t ck /2) + 1 ns max; for adsp-2 1062l, specification is (t ck /2) C 1.5 ns min, (t ck /2) + 1 ns max; for adsp-21060c specification is (t ck /2) C 2.25 ns min, (t ck /2) + 1 ns max. 6 for adsp-21062, specification is (t ck /2) + 8.75 ns min, (3 t ck /2) + 17 ns max; for adsp-2 1062l, specification is (t ck /2) + 8 ns min, (3 t ck /2) + 17 ns max; for adsp-21060lc specification is (t ck /2) + 8 ns min, (3 t ck /2) + 18.5 ns max.
rev. g | page 40 of 64 | august 2010 adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc link ports 2 clk speed operation calculation of link receiver data setup and hold relative to link clock is required to determin e the maximum allowable skew that can be introduced in the transmission path between ldata and lclk. setup skew is the maximum delay that can be introduced in ldata relative to lclk: setup skew = t lclktwh min C t dldch C t sldcl hold skew is the maximum dela y that can be introduced in lclk relative to ldata: hold skew = t lclktwl min C t hldch C t hldcl calculations made directly from 2 speed specifications will result in unrealistically small skew times because they include multiple tester guardbands. note that link port transfers at 2 clk speed at 40 mhz (t ck = 25 ns) may fail. however, 2 clk speed link port trans- fers at 33 mhz (t ck = 30 ns) work as specified. table 25. link port service request interrupts:1 and 2 speed operations 5 v 3.3 v unit parameter min max min max timing requirements t slck lack/lclk setup before clkin low 1 10 10 ns t hlck lack/lclk hold after clkin low 1 22n s 1 only required for interrupt recognition in the current cycle. table 26. link portsreceive 5 v 3.3 v unit parameter min max min max timing requirements t sldcl data setup before lclk low 2.5 2.25 ns t hldcl data hold after lclk low 2.25 2.25 ns t lclkiw lclk period (2 operation) t ck /2 t ck /2 ns t lclkrwl lclk width low 1 4.5 5.25 ns t lclkrwh lclk width high 2 4.25 4 ns switching characteristics t dlahc lack high delay after clkin high 3 18 + dt/2 28.5 + dt/2 18 + dt/2 29.5 + dt/2 ns t dlalc lack low delay after lclk high 4 61 661 6n s 1 for adsp-21060l, specif ication is 5 ns min. 2 for adsp-21062, specification is 4 ns min, for adsp-21060lc, specification is 4.5 ns min. 3 lack goes low with t dlalc relative to rise of lclk af ter first nibble, but does not go low if the receivers link buffer is not about to fill. 4 for adsp-21060l, specification is 6 ns min, 18 ns max. for adsp-2 1060c, specification is 6 ns min, 16.5 ns max. for adsp-21060l c, specification is 6 ns min, 18.5 ns max.
adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc rev. g | page 41 of 64 | august 2010 table 27. link portstransmit 5 v 3.3 v unit parameter min max min max timing requirements t slach lack setup before lclk high 19 19 ns t hlach lack hold after lclk high C6.75 C6.5 ns switching characteristics t dlclk data delay after clkin 8 8 ns t dldch data delay after lclk high 1 2.25 2.25 ns t hldch data hold after lclk high 2 C2.0 C2 ns t lclktwl lclk width low 3 (t ck /4) C 1 (t ck /4) + 1.25 (t ck /4) C 0.75 (t ck /4) + 1.5 ns t lclktwh lclk width high 4 (t ck /4) C 1.25 (t ck /4) + 1 (t ck /4) C 1.5 (t ck /4) + 1 ns t dlaclk lclk low delay after lack high (t ck /4) + 9 (3 t ck /4) + 16.5 (t ck /4) + 9 (3 t ck /4) + 16.5 ns 1 for adsp-21060/adsp-21060c, specification is 2.5 ns max. 2 for adsp-21062l, specific ation is C2.25 ns min. 3 for adsp-21060, specification is (t ck /4) C 1ns min, (t ck /4) + 1 ns max; for adsp-21060c /adsp-21062l, specification is (t ck /4) C 1 ns min, (t ck /4) + 1.5 ns max. 4 for adsp-21060, specification is (t ck /4) C 1 ns min, (t ck /4) + 1 ns max; for adsp-2 1060c, specification is (t ck /4) C 1.5 ns min, (t ck /4) + 1 ns max.
rev. g | page 42 of 64 | august 2010 adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc figure 24. link portsreceive clkin lclk ldat( 3 :0) lack lclk 1x or lclk 2x clkin ldat( 3 :0) lack (in) lclk 1x or lclk 2x ldat( 3 :0) lack (out) the t s lach requirement applie s to the ri s ing edge of lclk only for the fir s t nibble tran s mitted. clkin tran s mit t dldch t hldch t dlclk t lclktwh t lclktwl t s lach t hlach t dlaclk t s ldcl t hldcl t lclkrwh t dlahc t dlalc link port enable or three- s tate take s effect 2 cycle s afterawritetoalinkportcontrolregi s ter. t endlk t tdlk receive link port enable/three- s tate delay from in s truction t lclkrwl t lclkiw clkin t s lck t hlck link port interrupt s etup time lclk la s tnibble tran s mitted fir s tnibble tran s mitted lclk inactive (high) out in lack
adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc rev. g | page 43 of 64 | august 2010 serial ports for serial ports, see table 28 , table 29 , table 30 , table 31 , table 32 , table 33 , table 35 , figure 26 , and figure 25 . to deter- mine whether communication is possible between two devices at clock speed n, the following sp ecifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) sclk width. table 28. serial portsexternal clock parameter 5 v and 3.3 v min max unit timing requirements t sfse tfs/rfs setup before tclk/rclk 1 3.5 ns t hfse tfs/rfs hold after tclk/rclk 1, 2 4n s t sdre receive data setup before rclk 1 1.5 ns t hdre receive data hold after rclk 1 6.5 ns t sclkw tclk/rclk width 3 9n s t sclk tclk/rclk period t ck ns 1 referenced to sample edge. 2 rfs hold after rck when mce = 1, mfd = 0 is 0 ns minimum from drive edge. tfs hold after tck fo r late external tfs is 0 ns mini mum from drive edge. 3 for adsp-21060/adsp-21060c/adsp-21060l c, specification is 9.5 ns min. table 29. serial portsinternal clock parameter 5 v and 3.3 v min max unit timing requirements t sfsi tfs setup before tclk 1 ; rfs setup before rclk 1 8n s t hfsi tfs/rfs hold after tclk/rclk 1, 2 1n s t sdri receive data setup before rclk 1 3n s t hdri receive data hold after rclk 1 3n s 1 referenced to sample edge. 2 rfs hold after rck when mce = 1, mfd = 0 is 0 ns minimum from drive edge. tfs hold after tck fo r late external tfs is 0 ns mini mum from drive edge. table 30. serial portsexternal or internal clock parameter 5 v and 3.3 v min max unit switching characteristics t dfse rfs delay after rclk (internally generated rfs) 1 13 ns t hofse rfs hold after rclk (i nternally generated rfs) 1 3n s 1 referenced to drive edge. table 31. serial portsexternal clock parameter 5 v and 3.3 v min max unit switching characteristics t dfse tfs delay after tclk (internally generated tfs) 1 13 ns t hofse tfs hold after tclk (internally generated tfs) 1 3n s t ddte transmit data delay after tclk 1 16 ns t hdte transmit data hold after tclk 1 5n s 1 referenced to drive edge.
rev. g | page 44 of 64 | august 2010 adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc table 32. serial portsinternal clock parameter min max unit switching characteristics t dfsi tfs delay after tclk (internally generated tfs) 1 4.5 ns t hofsi tfs hold after tclk (internally generated tfs) 1 C1.5 ns t ddti transmit data delay after tclk 1 7.5 ns t hdti transmit data hold after tclk 1 0n s t sclkiw tclk/rclk width 2 0.5t sclk C2.5 0.5t sclk +2.5 ns 1 referenced to drive edge. 2 for adsp-21060l/adsp-21060 c, specification is 0.5 tsclk C 2 ns min, 0.5t sclk + 2 ns max. table 33. serial portsenable and three-state parameter min max unit switching characteristics t ddten data enable from external tclk 1, 2 4n s t ddtte data disable from external tclk 1, 3 10.5 ns t ddtin data enable from internal tclk 1 0n s t ddtti data disable from internal tclk 1, 4 3n s t dclk tclk/rclk delay from clkin 22 + 3 dt/8 ns t dptr sport disable after clkin 17 ns 1 referenced to drive edge. 2 for adsp-21060l/adsp-21060c, specif ication is 3.5 ns min; for adsp-2 1062 specification is 4.5 ns min. 3 for adsp-21062l, specific ation is 16 ns max. 4 for adsp-21062l, specification is 7.5 ns max. table 34. serial portsgated sclk with external tfs (mesh multiprocessing) 1 parameter min max unit switching characteristics t stfsck tfs setup before clkin 4 ns t htfsck tfs hold after clkin t ck /2 ns 1 applies only to gated serial clock mode used for serial port system i/o in mesh multiprocessing systems. table 35. serial portsexternal late frame sync parameter min max unit switching characteristics t ddtlfse data delay from late external tf s or external rfs with mce = 1, mfd = 0 1, 2 12 ns t ddtenfs data enable from late fs or mce = 1, mfd = 0 1, 3 3.5 ns 1 mce = 1, tfs enable and tfs valid follow t ddtlfse and t ddtenfs . 2 for adsp-21062/adsp-21 062l, specification is 12.75 ns max; for adsp-210 60l/adsp-21060lc, specific ation is 12.8 ns max. 3 for adsp-21060/adsp-2 1060c, specificat ion is 3 ns min.
adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc rev. g | page 45 of 64 | august 2010 figure 25. serial ports dt dt drive edge drive edge drive edge drive edge tclk/rclk tclk (int) tclk/rclk tclk (ext) rclk rf s dr drive edge s ample edge data receive internal clock data receive external clock rclk rf s dr drive edge s ample edge note: either the ri s ing edge or falling edge of rclk, tclk can be u s ed a s the active s ampling edge. tclk tf s dt drive edge s ample edge tclk tfs dt drive edge s ample edge data tran s mit internal clock data tran s mit external clock note: either the ri s ing edge or falling edge of rclk, tclk can be u s ed a s the active s ampling edge. t ddtte t ddten t ddtti t ddtin t s dri t hdri t s f s i t hf s i t df s e t hof s e t s clkiw t s dre t hdre t s f s e t hf s e t df s e t s clkw t hof s e t ddti t hdti t s f s i t hf s i t s clkiw t df s i t hof s i t ddte t hdte t s f s e t hf s e t df s e t s clkw t hof s e clkin t dptr s port di s able delay from in s truction tclk, rclk tf s ,rf s ,dt tclk (int) rclk (int) s port enable and three- s tate latency i s two cycle s t dclk low to high only t s tf s ck clkin t htf s ck note: applie s only to gated s erial clock mode with external tf s ,a s u s ed in the s erial port s y s tem i/o for me s hmultiproce ss ing. tf s (ext)
rev. g | page 46 of 64 | august 2010 adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc figure 26. serial portsexternal late frame sync drive s ample drive tclk tf s dt drive s ample drive late external tf s external rf s with mce = 1, mfd = 0 1 s t bit 2nd bit dt rclk rf s 1 s t bit 2nd bit t hof s e/i t s f s e/i t ddte/i t ddtenf s t ddtlf s e t hdte/i t hof s e/i t s f s e/i t ddte/i tddtenf s t ddtlf s e t hdte/i
adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc rev. g | page 47 of 64 | august 2010 jtag test access port and emulation for jtag test access port and emulation, see table 36 and figure 27 . table 36. jtag test access port and emulation parameter min max unit timing requirements t tck tck period t ck ns t stap tdi, tms setup before tck high 5 ns t htap tdi, tms hold after tck high 6 ns t ssys system inputs setup before tck low 1 7n s t hsys system inputs hold after tck low 1, 2 18 ns t trstw trst pulse width 4t ck ns switching characteristics t dtdo tdo delay from tck low 13 ns t dsys system outputs delay after tck low 3 18.5 ns 1 system inputs = data63C0, addr31C0, rd , wr , ack, sbts , hbr , hbg , cs , dmar1 , dmar2 , br 6C1, id2C0, rpba, irq2C0 , flag3C0, pa , brst, dr0, dr1, tclk0, tclk1, rclk0, rclk1, tfs0, tfs1, rfs0, rfs1, lxdat7C0, lxclk, lxack, eboot, lboot, bms , clkin, reset . 2 for adsp-21060l/adsp-21060 lc/adsp-21062l, specific ation is 18.5 ns min. 3 system outputs = data63C0, addr31C0, ms3C0 , rd , wr , ack, page, clkout, hbg , redy, dmag1 , dmag2 , br6C1 , pa , brst, cif , flag3C0, timexp, dt0, dt1, tclk0, tclk1, rclk0, rclk1, tfs0, tfs1, rfs0, rfs1, lxdat7C0, lxclk, lxack, bms . figure 27. jtag test ac cess port and emulation tc tm s s s s s s s s ss s s s s s
rev. g | page 48 of 64 | august 2010 adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc test conditions for the ac signal specifications (timing parameters), see timing specifications on page 21 . these specifications include output disable time, output enable time , and capacitive loading. the timing specifications for the ds p apply for the voltage reference levels in figure 28 . output disable time output pins are considered to be disabled when they stop driv- ing, go into a high impedance stat e, and start to decay from their output high or low voltage. the time for the voltage on the bus to decay by v is dependent on the capacitive load, c l , and the load current, i l . this decay time can be approximated by the fol- lowing equation: the output disable time t dis is the difference between t measured and t decay as shown in figure 29 . the time t measured is the interval from when the refere nce signal switches to when the output voltage decays v from the measured output high or output low voltage. t decay is calculated with test loads c l and i l , and with v equal to 0.5 v. output enable time output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driv- ing. the output enable time t ena is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the output enable/disable diagram ( figure 29 ). if multiple pins (such as the data bus) ar e enabled, the measurement value is that of the first pin to start driving. example system hold time calculation to determine the data output hold time in a particular system, first calculate t decay using the equation given above. choose v to be the difference between th e adsp-2106xs output voltage and the input threshold for the device requiring the hold time. a typical v will be 0.4 v. c l is the total bus capacitance (per data line), and i l is the total leakage or three-state current (per data line). the hold time will be t decay plus the minimum disable time (i.e., t datrwh for the write cycle). capacitive loading output delays and holds are based on standard capacitive loads: 50 pf on all pins (see figure 30 ). the delay and hold specifica- tions given should be derated by a factor of 1.5 ns/50 pf for loads other than the nominal value of 50 pf. figure 32 , figure 33 , figure 37 , and figure 38 show how output rise time varies with capacitance. figure 34 and figure 36 show graphically how output delays an d holds vary with load capaci- tance. (note that this graph or de rating does not apply to output disable delays; see the previous section output disable time under test conditions.) the graphs of figure 32 , figure 33 , figure 37 , and figure 38 may not be linear outside the ranges shown. output drive characteristics figure 31 shows typical i-v characteristics for the output driv- ers of the adsp-2106x. the curves represent the current drive capability of the output drivers as a function of output voltage. figure 28. voltage reference levels for ac measurements (except output enable/disable) figure 29. output enable/disable iput or output 1.5v 1.5v p ext c l v i l ------------- - = reference s s s s s s s s s s s s s s s s s s figure 30. equivalent device loading for ac measurements (includes all fixtures) 1.5v 50pf to output pi i ol i oh
adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc rev. g | page 49 of 64 | august 2010 output characteristics (5 v) figure 31. adsp-21062 typical output drive currents (v dd = 5 v) figure 32. typical output rise time (10% to 90% v dd ) vs. load capacitance (v dd = 5 v) s ource voltage - v - 75 - 150 05.25 s o u r c e c u r r e n t - m a 0.75 1.50 2.25 3 .00 3 .75 4.50 75 - 50 - 100 - 125 25 - 25 50 0 4.75v, +100c 4.75v,+100c 5.0v, +25c 5.25v, - 40c 5.0v, +25c 5.25v, - 40c load capacitance - pf 16.0 8 .0 0 0200 20 40 60 8 0 100 120 140 160 1 8 0 14.0 12.0 4.0 2.0 10.0 6.0 fall tim e ri s etime r i s e a n d f a l l t i m e s - n s ( 0 . 5 v t o 4 . 5 v , 1 0 % t o 9 0 % ) y = 0.005x + 3 .7 y = 0.00 3 1x + 1.1 figure 33. typical output rise time (0.8 v to 2.0 v) vs. load capacitance (v dd = 5 v) figure 34. typical output delay or hold vs. load capacitance (at maximum case temperature) (v dd = 5 v) 3 .5 0 r i s e a n d f a l l t i m e s - n s ( 0 . 8 v t o 2 . 0 v ) 3 .0 2.5 2.0 1.5 1.0 0.5 load capacitance - pf 0200 20 40 60 8 0 100 120 140 160 1 8 0 fall time ri s etime y = 0.009x + 1.1 y=0.005x+0.6 load capacitance - pf o u t p u t d e l a y o r h o l d - n s 5 - 1 25 200 50 75 100 125 150 175 4 3 2 1 nominal y=0.0 3 x - 1.45
rev. g | page 50 of 64 | august 2010 adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc output characteristics (3.3 v) figure 35. adsp-21062 typical output drive currents (v dd = 3.3 v) figure 36. typical output delay or hold vs. load capacitance (at maximum case temperature) (v dd = 3.3 v) s ource voltage - v 120 - 20 - 8 0 0 3 .5 s o u r c e c u r r e n t - m a 0.5 1.0 1.5 2.0 2.5 3 .0 100 0 - 40 - 60 60 20 8 0 40 - 100 - 120 3 .0v, + 8 5c 3 . 3 v, +25c 3 .6v, - 40c 3 .6v, - 40c 3 . 3 v, +25c 3 .0v, + 8 5c v oh v ol load capacitance - pf o u t p u t d e l a y o r h o l d - n s 5 - 1 25 200 50 75 100 125 150 175 4 3 2 1 nominal y=0.0 3 29x - 1.65 figure 37. typical output rise time (10% to 90% v dd ) vs. load capacitance (v dd = 3.3 v) figure 38. typical output rise time (0.8 v to 2.0 v) vs. load capacitance (v dd = 3.3 v) load capacitance - pf 0 2 0 20 40 60 8 0 100 120 y = 0.0796x + 1.17 y = 0.0467x + 0.55 ri s etime fall time 140 160 1 8 0 200 4 6 8 10 12 14 16 1 8 r i s e a n d f a l l t i m e s - n s ( 1 0 % t o 9 0 % ) load capacitance - pf 0 0 20 40 60 8 0 100 120 y=0.0 3 91x + 0. 3 6 y=0.0 3 05x + 0.24 ris etime fall time 140 160 1 8 0200 r i s e a n d f a l l t i m e s - n s ( 0 . 8 v t o 2 . 0 v ) 1 2 3 4 5 6 7 8 9
adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc rev. g | page 51 of 64 | august 2010 environmental conditions the adsp-2106x processors are rated for performance under t case environmental conditions specified in the operating con- ditions (5 v) on page 15 and operating conditions (3.3 v) on page 18 . thermal characteristics for mqfp_pq4 and pbga packages the adsp-21060/adsp-21060l and adsp-21062/adsp- 21062l are available in 240-lead thermally enhanced mqfp_pq4 and 225-ball plastic ball grid array packages. the top surface of the thermally en hanced mqfp_pq4 contains a metal slug from which most of the die heat is dissipated. the slug is flush with the top surface of the package. note that the metal slug is internally connected to gnd through the device substrate. both packages are specifie d for a case temperature (t case ). to ensure that the t case is not exceeded, a heatsink and/or an air- flow source may be used. a heatsi nk should be attached with a thermal adhesive. t case = t amb + (pd ca ) t case = case temperature (measure d on top surface of package) pd =power dissipation in w (thi s value depends upon the spe- cific application; a method for calculating pd is shown under power dissipation). ca =value from table 37 below. thermal characteristics for cqfp package the adsp-21060c/adsp-21060lc ar e available in 240-lead thermally enhanced ceramic qf p (cqfp). there are two pack- age versions, one with a copper/tungsten heat slug on top of the package (cz) for air cooling, and one with the heat slug on the bottom (cw) for cooling thro ugh the board. the adsp-2106x is specified for a case temperature (t case ). to ensure that the t case data sheet specification is not exceeded, a heatsink and/or an air flow source may be used. a heatsink should be attached with a thermal adhesive. t case = t amb + (pd ca ) t case = case temperature (measure d on top surface of package) pd = power dissipation in w (t his value depends upon the spe- cific application; a method for calculating pd is shown under power dissipation). ca =value from table 38 below. table 37. thermal characteristics for thermally enhanced 240-lead mqfp_pq4 1 1 this represents thermal resistance at total power of 5 w. with airflow, no variance is seen in ca at 5 w. ca at 0 lfm varies with power: at 2 w, ca = 14c/w at 3 w, ca = 11c/w parameter airflow (lfm 2 ) 2 lfm = linear feet per minute of airflow. typical unit ca 01 0 c / w ca 100 9 c/w ca 200 8 c/w ca 400 7 c/w ca 600 6 c/w table 38. thermal characteristics for bga parameter airflow (lfm 1 ) 1 lfm = linear feet per minute of airflow. typical unit ca 02 0 . 7 0 c / w ca 200 15.30 c/w ca 400 12.90 c/w table 39. thermal characteristics for thermally enhanced 240-lead cqfp 1 1 this represents thermal resistance at total power of 5 w. with airflow, no variance is seen in ca at 5w. ca at 0 lfm varies with power. adsp-21060cw/adsp-21060lcw: at 2 w, ca = 23c/w at 3 w, ca = 21.5c/w adsp-21060cz/adsp-21060lcz: at 2 w, ca = 24c/w at 3 w, ca = 21.5c/w jc = 0.24c/w for all cqfp models. parameter airflow (lfm 2 ) 2 lfm = linear feet per minute of airflow. typical unit adsp-21060cw/adsp-21060lcw ca 0 19.5 c/w ca 100 16 c/w ca 200 14 c/w ca 400 12 c/w ca 600 10 c/w adsp-21060cz/adsp-21060lcz ca 0 20 c/w ca 100 16 c/w ca 200 14 c/w ca 400 11.5 c/w ca 600 9.5 c/w
rev. g | page 52 of 64 | august 2010 adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc 225-ball pbga ball configuration table 40. adsp-2106x 225-ball metric pbga ball assignments (b-225-2) ball name ball number ball name ball number ball name ball number ball name ball number ball name ball number bms a01 addr25 d01 addr14 g01 addr6 k01 emu n01 addr30 a02 addr26 d02 addr15 g02 addr5 k02 tdo n02 dmar2 a03 ms2 d03 addr16 g03 addr3 k03 irq0 n03 dt1 a04 addr29 d04 addr19 g04 addr0 k04 irq1 n04 rclk1 a05 dmar1 d05 gnd g05 icsa k05 id2 n05 tclk0 a06 tfs1 d06 v dd g06 gnd k06 l5dat1 n06 rclk0 a07 cpa d07 v dd g07 v dd k07 l4clk n07 adrclk a08 hbg d08 v dd g08 v dd k08 l3clk n08 cs a09 dmag2 d09 v dd g09 v dd k09 l3dat3 n09 clkin a10 br5 d10 v dd g10 gnd k10 l2dat0 n10 page a11 br1 d11 gnd g11 gnd k11 l1ack n11 br3 a12 data40 d12 data22 g12 data8 k12 l1dat3 n12 data47 a13 data37 d13 data25 g13 data11 k13 l0dat3 n13 data44 a14 data35 d14 data24 g14 data13 k14 data1 n14 data42 a15 data34 d15 data23 g15 data14 k15 data3 n15 ms0 b01 addr21 e01 addr12 h01 addr2 l01 trst p01 sw b02 addr22 e02 addr11 h02 addr1 l02 tms p02 addr31 b03 addr24 e03 addr13 h03 flag0 l03 eboot p03 hbr b04 addr27 e04 addr10 h04 flag3 l04 id0 p04 dr1 b05 gnd e05 gnd h05 rpba l05 l5clk p05 dt0 b06 gnd e06 v dd h06 gnd l06 l5dat3 p06 dr0 b07 gnd e07 v dd h07 gnd l07 l4dat0 p07 redy b08 gnd e08 v dd h08 gnd l08 l4dat3 p08 rd b09 gnd e09 v dd h09 gnd l09 l3dat2 p09 ack b10 gnd e10 v dd h10 gnd l10 l2clk p10 br6 b11 nc e11 gnd h11 nc l11 l2dat2 p11 br2 b12 data33 e12 data18 h12 data4 l12 l1dat0 p12 data45 b13 data30 e13 data19 h13 data7 l13 l0ack p13 data43 b14 data32 e14 data21 h14 data9 l14 l0dat1 p14 data39 b15 data31 e15 data20 h15 data10 l15 data0 p15 ms3 c01 addr17 f01 addr9 j01 flag1 m01 tck r01 ms1 c02 addr18 f02 addr8 j02 flag2 m02 irq2 r02 addr28 c03 addr20 f03 addr7 j03 timexp m03 reset r03 sbts c04 addr23 f04 addr4 j04 tdi m04 id1 r04 tclk1 c05 gnd f05 gnd j05 lboot m05 l5dat0 r05 rfs1 c06 gnd f06 v dd j06 l5ack m06 l4ack r06 tfs0 c07 v dd f07 v dd j07 l5dat2 m07 l4dat1 r07 rfs0 c08 v dd f08 v dd j08 l4dat2 m08 l3ack r08 wr c09 v dd f09 v dd j09 l3dat0 m09 l3dat1 r09 dmag1 c10 gnd f10 v dd j10 l2dat3 m10 l2ack r10 br4 c11 gnd f11 gnd j11 l1dat1 m11 l2dat1 r11 data46 c12 data29 f12 data12 j12 l0dat0 m12 l1clk r12 data41 c13 data26 f13 data15 j13 data2 m13 l1dat2 r13 data38 c14 data28 f14 data16 j14 data5 m14 l0clk r14 data36 c15 data27 f15 data17 j15 data6 m15 l0dat2 r15
adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc rev. g | page 53 of 64 | august 2010 figure 39. adsp-21060/adsp-21062 pbga ball assignments (top view, summary) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r adrclk bms addr30 dmar2 dt1 rclk1 tclk0 rclk0 cs clkin pag e br3 data47 data44 data42 ms0 sw addr31 hbr dr1 dt0 dr0 redy rd ack br6 br2 data45 data43 data39 ms3 ms1 addr28 sbts tclk1 rfs1 tfs0 rfs0 wr dmag1 br4 data46 data41 data38 data36 addr25 addr26 ms2 addr29 dmar1 tfs1 cpa hbg dmag2 br5 br1 data40 data37 data35 data34 addr21 addr22 addr24 addr27 gnd gnd gnd gnd gnd gnd nc data33 data30 data32 data31 addr17 addr18 addr20 addr23 gnd gnd vdd vdd vdd gnd gnd data29 data26 data28 data27 addr14 addr15 addr16 addr19 gnd vdd vdd vdd vdd vdd gnd data22 data25 data24 data23 addr12 addr11 addr13 addr10 gnd vdd vdd vdd vdd vdd gnd data18 data19 data21 data20 addr9 addr8 addr7 addr4 gnd vdd vdd vdd vdd vdd gnd data12 data15 data16 data17 addr6 addr5 addr3 addr0 icsa gnd vdd vdd vdd gnd gnd data8 data11 data13 data14 addr2 addr1 flag0 flag3 rpba gnd gnd gnd gnd gnd nc data4 data7 data9 data10 flag1 flag2 timexp tdi lboot l5ack l5dat2 l4dat2 l3dat0 l2dat3 l1dat1 l0dat0 data2 data5 data6 emu tdo irq0 irq1 id2 l5dat1 l4clk l3clk l3dat3 l2dat0 l1ack l1dat3 l0dat3 data1 data3 trst tms eboot id0 l5clk l5dat3 l4dat0 l4dat3 l3dat2 l2clk l2dat2 l1dat0 l0ack l0dat1 data0 tck irq2 reset id1 l5dat0 l4ack l4dat1 l3ack l0dat2 l0clk l1dat2 l1clk l2dat1 l2ack l3dat1
rev. g | page 54 of 64 | august 2010 adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc 240-lead mqfp_pq4/c qfp pin configuration table 41. adsp-2106x mqfp_pq4 and adsp-21060cz cqfp pin assignments (sp-240-2, qs-240-2a, qs-240-2b) pin name pin no. pin name pin no. pin name pin no. pin name pin no. pin name pin no. pin name pin no. tdi 1 addr20 41 tclk0 81 data41 121 data14 161 l2dat0 201 trst 2 addr21 42 tfs0 82 data40 122 data13 162 l2clk 202 v dd 3gnd 43 dr0 83 data39 123 data12 163 l2ack 203 tdo 4 addr22 44 rclk0 84 v dd 124 gnd 164 nc 204 timexp 5 addr23 45 rfs0 85 data38 125 data11 165 v dd 205 emu 6addr2446v dd 86 data37 126 data10 166 l3dat3 206 icsa 7 v dd 47 v dd 87 data36 127 data9 167 l3dat2 207 flag3 8 gnd 48 gnd 88 gnd 128 v dd 168 l3dat1 208 flag2 9 v dd 49 adrclk 89 nc 129 data8 169 l3dat0 209 flag1 10 addr25 50 redy 90 data35 130 data7 170 l3clk 210 flag011addr2651hbg 91 data34 131 data6 171 l3ack 211 gnd12addr2752cs 92 data33 132 gnd 172 gnd 212 addr0 13 gnd 53 rd 93 v dd 133 data5 173 l4dat3 213 addr1 14 ms3 54 wr 94 v dd 134 data4 174 l4dat2 214 v dd 15 ms2 55 gnd 95 gnd 135 data3 175 l4dat1 215 addr2 16 ms1 56 v dd 96 data32 136 v dd 176 l4dat0 216 addr3 17 ms0 57 gnd 97 data31 137 data2 177 l4clk 217 addr4 18 sw 58 clkin 98 data30 138 data1 178 l4ack 218 gnd 19 bms 59 ack 99 gnd 139 data0 179 v dd 219 addr520addr2860dmag2 100 data29 140 gnd 180 gnd 220 addr6 21 gnd 61 dmag1 101 data28 141 gnd 181 v dd 221 addr7 22 v dd 62 page 102 data27 142 l0dat3 182 l5dat3 222 v dd 23 v dd 63 v dd 103 v dd 143 l0dat2 183 l5dat2 223 addr824addr2964br6 104 v dd 144 l0dat1 184 l5dat1 224 addr925addr3065br5 105 data26 145 l0dat0 185 l5dat0 225 addr10 26 addr31 66 br4 106 data25 146 l0clk 186 l5clk 226 gnd 27 gnd 67 br3 107 data24 147 l0ack 187 l5ack 227 addr11 28 sbts 68 br2 108 gnd 148 v dd 188 gnd 228 addr12 29 dmar2 69 br1 109 data23 149 l1dat3 189 id2 229 addr13 30 dmar1 70 gnd 110 data22 150 l1dat2 190 id1 230 v dd 31 hbr 71 v dd 111 data21 151 l1dat1 191 id0 231 addr14 32 dt1 72 gnd 112 v dd 152 l1dat0 192 lboot 232 addr15 33 tclk1 73 data47 113 data20 153 l1clk 193 rpba 233 gnd 34 tfs1 74 data46 114 data19 154 l1ack 194 reset 234 addr16 35 dr1 75 data45 115 data18 155 gnd 195 eboot 235 addr17 36 rclk1 76 v dd 116 gnd 156 gnd 196 irq2 236 addr18 37 rfs1 77 data44 117 data17 157 v dd 197 irq1 237 v dd 38 gnd 78 data43 118 data16 158 l2dat3 198 irq0 238 v dd 39 cpa 79 data42 119 data15 159 l2dat2 199 tck 239 addr19 40 dt0 80 gnd 120 v dd 160 l2dat1 200 tms 240
adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc rev. g | page 55 of 64 | august 2010 table 42. adsp-21060cw/21060lcw cqfp pin assignments (qs-240-1a, qs-240-1b) pin name pin no. pin name pin no. pin name pin no. pin name pin no. pin name pin no. pin name pin no. gnd 1 data29 41 dmag2 81 addr28 121 addr5 161 gnd 201 data0 2 gnd 42 ack 82 bms 122 gnd 162 v dd 202 data1 3 data30 43 clkin 83 sw 123 addr4 163 l4ack 203 data2 4 data31 44 gnd 84 ms0 124 addr3 164 l4clk 204 v dd 5data3245v dd 85 ms1 125 addr2 165 l4dat0 205 data3 6 gnd 46 gnd 86 ms2 126 v dd 166 l4dat1 206 data4 7 v dd 47 wr 87 ms3 127 addr1 167 l4dat2 207 data5 8 v dd 48 rd 88 gnd 128 addr0 168 l4dat3 208 gnd 9 data33 49 cs 89 addr27 129 gnd 169 gnd 209 data610data3450hbg 90 addr26 130 flag0 170 l3ack 210 data7 11 data35 51 redy 91 addr25 131 flag1 171 l3clk 211 data812nc 52adrclk92v dd 132 flag2 172 l3dat0 212 v dd 13 gnd 53 gnd 93 gnd 133 flag3 173 l3dat1 213 data914data3654v dd 94 v dd 134 icsa 174 l3dat2 214 data10 15 data37 55 v dd 95 addr24 135 emu 175 l3dat3 215 data11 16 data38 56 rfs0 96 addr23 136 timexp 176 v dd 216 gnd 17 v dd 57 rclk0 97 addr22 137 tdo 177 nc 217 data12 18 data39 58 dr0 98 gnd 138 v dd 178 l2ack 218 data13 19 data40 59 tfs0 99 addr21 139 trst 179 l2clk 219 data14 20 data41 60 tclk0 100 addr20 140 tdi 180 l2dat0 220 v dd 21 gnd 61 dt0 101 addr19 141 tms 181 l2dat1 221 data15 22 data42 62 cpa 102 v dd 142 tck 182 l2dat2 222 data16 23 data43 63 gnd 103 v dd 143 irq0 183 l2dat3 223 data17 24 data44 64 rfs1 104 addr18 144 irq1 184 v dd 224 gnd 25 v dd 65 rclk1 105 addr17 145 irq2 185 gnd 225 data18 26 data45 66 dr1 106 addr16 146 eboot 186 gnd 226 data19 27 data46 67 tfs1 107 gnd 147 reset 187 l1ack 227 data20 28 data47 68 tclk1 108 addr15 148 rpba 188 l1clk 228 v dd 29 gnd 69 dt1 109 addr14 149 lboot 189 l1dat0 229 data21 30 v dd 70 hbr 110 v dd 150 id0 190 l1dat1 230 data22 31 gnd 71 dmar1 111 addr13 151 id1 191 l1dat2 231 data23 32 br1 72 dmar2 112 addr12 152 id2 192 l1dat3 232 gnd 33 br2 73 sbts 113 addr11 153 gnd 193 v dd 233 data24 34 br3 74 gnd 114 gnd 154 l5ack 194 l0ack 234 data25 35 br4 75 addr31 115 addr10 155 l5clk 195 l0clk 235 data26 36 br5 76 addr30 116 addr9 156 l5dat0 196 l0dat0 236 v dd 37 br6 77 addr29 117 addr8 157 l5dat1 197 l0dat1 237 v dd 38 v dd 78 v dd 118 v dd 158 l5dat2 198 l0dat2 238 data27 39 page 79 v dd 119 addr7 159 l5dat3 199 l0dat3 239 data28 40 dmag1 80 gnd 120 addr6 160 v dd 200 gnd 240
rev. g | page 56 of 64 | august 2010 adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc outline dimensions figure 40. 225-ball plastic ball grid array [pbga] (b-225-2) dimensions shown in millimeters compliant to jedec standards ms-034-aaj-2 2.70 max 1.27 bsc 18.00 bsc sq a b c d e f g h j k l m n p r 15 14 13 12 11 10 9 8 7 6 5 42 31 top view 1.30 1.20 1.10 0.15 max coplanarity 0.70 0.60 0.50 detail a 0.90 0.75 0.60 ball diameter bottom view detail a a1 corner index area 20.10 20.00 sq 19.90 23.20 23.00 sq 22.80 ball a1 indicator 0.50 r 3 places seating plane
adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc rev. g | page 57 of 64 | august 2010 figure 41. 240-lead metric quad flat package, thermally en hanced powerquad [mqfp_pq4] (sp-240-2) dimensions shown in millimeters compliant with jedec standards ms-029-ga 0.66 0.56 0.46 4.10 3.78 3.55 seating plane view a 0.38 0.25 0.20 0.09 0.076 coplanarity 3.50 3.40 3.30 7 0 view a rotated 90 ccw 1 240 181 180 121 120 61 60 pin 1 heat slug top view (pins down) 34.60 bsc sq 29.50 ref sq 32.00 bsc sq 3.92 45 (4 places) 24.00 ref sq 0.27 max 0.17 min 0.50 bsc lead pitch
rev. g | page 58 of 64 | august 2010 adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc figure 42. 240-lead ceramic quad flat package, heat slug up [cqfp] (qs-240-2a) dimensions shown in millimeters 32.00 bsc sq 1 60 61 120 121 180 240 181 36.60 36.13 sq 35.65 28.05 27.80 sq 27.55 0.50 bsc 3.70 3.22 2.75 0.90 0.75 0.60 0.23 0.20 0.17 7 -3 180 181 1 240 120 121 60 61 19.00 ref sq bottom view (pins up) heat slug notes: 1. lead finish = gold plate 2. lead sweep/lead offset = 0.013mm max (sweep and/or offset can be used as the controlling dimension). lid seal ring top view (pins down) pin 1 indicator 4.30 3.62 2.95 0.60 0.40 0.20 view a 0.175 0.156 0.137 1.70 0.35 0.30 0.25 0.15 0.180 0.155 0.130 2.06 ref lead thickness 0.15 view a
adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc rev. g | page 59 of 64 | august 2010 figure 43. 240-lead ceramic quad flat package, mounte d with cavity down [cqfp] (qs-240-2b) dimensions shown in millimeters 65.90 bsc 75.50 bsc sq 121 180 181 240 1 60 120 61 index 1 gold plated 29.50 bsc top view 75.00 bsc sq 2.60 2.55 2.50 3.60 3.55 3.50 29.50 bsc 1 240 181 180 121 120 bottom view heat slug 60 61 index 2 1.50 dia no gold nonconductive ceramic tie bar 70.00 bsc sq 2.05 side view 0.50 0.90 0.80 0.70 3.42 3.17 2.92 1.22 (4) 16.50 (8 ) lid seal ring
rev. g | page 60 of 64 | august 2010 adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc figure 44. 240-lead cerami c quad flat package, heat slug down [cqfp] (qs-240-1a) dimensions shown in millimeters 32.00 bsc sq 1 60 61 120 121 180 240 lid seal ring top view (pins down) 181 36.60 36.13 sq 35.65 28.05 27.80 sq 27.55 0.50 bsc 3.70 3.22 2.75 0.90 0.75 0.60 0.23 0.20 0.17 7 -3 19.00 ref sq 180 181 1 240 120 121 60 61 bottom view (pins up) heat slug notes: 1. lead finish = gold plate 2. lead sweep/lead offset = 0.013mm max (sweep and/or offset can be used as the controlling dimension). 1.70 0.35 0.30 0.25 0.15 0.180 0.155 0.130 2.06 ref lead thickness 0.15 pin 1 indicator 4.20 3.52 2.85 0.50 0.30 0.10 view a view a 0.175 0.156 0.137
adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc rev. g | page 61 of 64 | august 2010 surface-mount design table 43 is provided as an aide to pcb design. for industry- standard design recommendations, refer to ipc-7351, generic requirements for surface-mount design and land pattern standard . figure 45. 240-lead ceramic quad flat package, mounted with cavity up [cqfp] (qs-240-1b) dimensions shown in millimeters 65.90 bsc 75.50 bsc sq 121 180 181 240 1 60 120 61 index 1 gold plated 29.50 bsc lid seal ring top view 75.00 bsc sq 2.60 2.55 2.50 3.60 3.55 3.50 29.50 bsc 1 240 181 180 121 120 bottom view heat slug 60 61 index 2 2.00 dia no gold nonconductive ceramic tie bar 70.00 bsc sq 2.05 side view 0.50 0.90 0.80 0.70 3.42 3.17 2.92 1.22 (4) 16.50 (8 ) table 43. bga data for use with surface-mount design package ball attach type solder mask opening ball pad size 225-ball grid array (pbga) solder mask defined 0.63 mm diameter 0.76 mm diameter
rev. g | page 62 of 64 | august 2010 adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc ordering guide model notes temperature range instruction rate on-chip sram operating voltage package description package option asdp-21060cz-133 1, 2 1 model refers to package with fo rmed leads. for model numbers of unformed lead versions (qs-240 -1b, qs-240-2b), contact analog d evices or an analog devices sales representative. 2 rohs compliant part. C40 c to +100 c 33 mhz 4m bit 5 v 240-lead cqfp [heat slug up] qs-240-2a asdp-21060cz-160 1, 2 C40 c to +100 c 40 mhz 4m bit 5 v 240-lead cqfp [heat slug up] qs-240-2a asdp-21060cw-133 1, 2 C40 c to +100 c 33 mhz 4m bit 5 v 240-lead cqfp [heat slug down] qs-240-1a asdp-21060cw-160 1, 2 C40 c to +100 c 40 mhz 4m bit 5 v 240-lead cqfp [heat slug down] qs-240-1a adsp-21060ks-133 0 c to 85 c 33 mhz 4m bit 5 v 240-lead mqfp_pq4 sp-240-2 adsp-21060ksz-133 2 0 c to 85 c 33 mhz 4m bit 5 v 240-lead mqfp_pq4 sp-240-2 adsp-21060ks-160 0 c to 85 c 40 mhz 4m bit 5 v 240-lead mqfp_pq4 sp-240-2 adsp-21060ksz-160 2 0 c to 85 c 40 mhz 4m bit 5 v 240-lead mqfp_pq4 sp-240-2 adsp-21060kb-160 0 c to 85 c 40 mhz 4m bit 5 v 225-ball pbga b-225-2 adsp-21060kbz-160 2 0 c to 85 c 40 mhz 4m bit 5 v 225-ball pbga b-225-2 adsp-21060lksz-133 2 0 c to 85 c 33 mhz 4m bit 3.3 v 240-lead mqfp_pq4 sp-240-2 adsp-21060lks-160 0 c to 85 c 40 mhz 4m bit 3.3 v 240-lead mqfp_pq4 sp-240-2 adsp-21060lksz-160 2 0 c to 85 c 40 mhz 4m bit 3.3 v 240-lead mqfp_pq4 sp-240-2 adsp-21060lkb-160 0 c to 85 c 40 mhz 4m bit 3.3 v 225-ball pbga b-225-2 adsp-21060lab-160 C40 c to +85 c 40 mhz 4m bit 3.3 v 225-ball pbga b-225-2 adsp-21060labz-160 2 C40 c to +85 c 40 mhz 4m bit 3.3 v 225-ball pbga b-225-2 ADSP-21060LCB-133 C40 c to +100 c 33 mhz 4m bit 3.3 v 225-ball pbga b-225-2 adsp-21060lcbz-133 2 C40 c to +100 c 33 mhz 4m bit 3.3 v 225-ball pbga b-225-2 asdp-21060lcw-160 1, 2 C40 c to +100 c 40 mhz 4m bit 3.3 v 240-lead cqfp [heat slug down] qs-240-1a adsp-21062ks-133 0 c to 85 c 33 mhz 2m bit 5 v 240-lead mqfp_pq4 sp-240-2 adsp-21062ksz-133 2 0 c to 85 c 33 mhz 2m bit 5 v 240-lead mqfp_pq4 sp-240-2 adsp-21062ks-160 0 c to 85 c 40 mhz 2m bit 5 v 240-lead mqfp_pq4 sp-240-2 adsp-21062ksz-160 2 0 c to 85 c 40 mhz 2m bit 5 v 240-lead mqfp_pq4 sp-240-2 adsp-21062kb-160 0 c to 85 c 40 mhz 2m bit 5 v 225-ball pbga b-225-2 adsp-21062kbz-160 2 0 c to 85 c 40 mhz 2m bit 5 v 225-ball pbga b-225-2 adsp-21062cs-160 C40 c to +100 c 40 mhz 2m bit 5 v 240-lead mqfp_pq4 sp-240-2 adsp-21062csz-160 2 C40 c to +100 c 40 mhz 2m bit 5 v 240-lead mqfp_pq4 sp-240-2 adsp-21062lks-133 0 c to 85 c 33 mhz 2m bit 3.3 v 240-lead mqfp_pq4 sp-240-2 adsp-21062lksz-133 2 0 c to 85 c 33 mhz 2m bit 3.3 v 240-lead mqfp_pq4 sp-240-2 adsp-21062lks-160 0 c to 85 c 40 mhz 2m bit 3.3 v 240-lead mqfp_pq4 sp-240-2 adsp-21062lksz-160 2 0 c to 85 c 40 mhz 2m bit 3.3 v 240-lead mqfp_pq4 sp-240-2 adsp-21062lkb-160 0 c to 85 c 40 mhz 2m bit 3.3 v 225-ball pbga b-225-2 adsp-21062lkbz-160 2 0 c to 85 c 40 mhz 2m bit 3.3 v 225-ball pbga b-225-2 adsp-21062lab-160 C40 c to 85 c 40 mhz 2m bit 3.3 v 225-ball pbga b-225-2 adsp-21062labz-160 2 C40 c to 85 c 40 mhz 2m bit 3.3 v 225-ball pbga b-225-2 adsp-21062lcs-160 C40 c to +100 c 40 mhz 2m bit 3.3 v 240-lead mqfp_pq4 sp-240-2 adsp-21062lcsz-160 2 C40 c to +100 c 40 mhz 2m bit 3.3 v 240-lead mqfp_pq4 sp-240-2
adsp-21060/adsp-21060l/adsp-21062/adsp-21062l/adsp-21060c/adsp-21060lc rev. g | page 63 of 64 | august 2010
rev. g | page 64 of 64 | august 2010 ? 2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d00167-0-8/10(g) adsp-21060/adsp-21060l/adsp-21062/ad sp-21062l/adsp-21060c/adsp-21060lc

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